SAR ADC Duty-Cycle Self-Test for Conversion Timing Margins
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Solution Overview
Problem
SAR ADCs face challenges in ensuring consistent conversion time due to variations from PVT (process-voltage-temperature) and layout parasitics, which can cause undue delays and require external testing equipment.
Innovation Solution
A circuit portion is integrated into the SAR ADC to generate and compare feedback and reference duty cycles, allowing for built-in testing by generating a digital representation of the conversion time, enabling self-testing without external equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SAR ADC conversion time is reduced to meet sampling rate requirements, then productivity is improved, but conversion accuracy may deteriorate due to insufficient conversion time under PVT variations
Solution Approach 1:
The patent performs preliminary measurement of the SAR ADC conversion time using the feedback signal duty cycle comparison before actual conversion operations. This preliminary action allows the system to know the conversion time characteristics under current PVT conditions, enabling proactive adjustment of timing margins to ensure both speed and accuracy requirements are met.
Solution Approach 2:
The patent implements a feedback mechanism where the SAR ADC output is fed back to measure the actual conversion time by comparing duty cycles. This feedback information is then used to adjust timing parameters and ensure that conversion accuracy is maintained while meeting sampling rate requirements, resolving the contradiction between speed and reliability.
2Measurement precision
If external test equipment is used to measure SAR ADC conversion time, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the SAR ADC to measure its own conversion time using built-in feedback signaling and duty cycle comparison circuitry. The system uses its own output signal fed back through a delay element and comparator to generate a measurement of its conversion time, eliminating the need for external test equipment while maintaining measurement precision.
Solution Approach 2:
The patent introduces an intermediary feedback signal path that carries timing information from the SAR ADC output back to the input side. This intermediary mechanism uses duty cycle comparison of the feedback signal with a reference signal to extract conversion time information, providing precise measurement without requiring complex external testing equipment.
3Adaptability or versatility
If SAR ADC conversion time varies due to PVT variations and layout parasitics, then adaptability is improved, but timing margin becomes unpredictable
Solution Approach 1:
The patent performs preliminary measurement of the actual conversion time using duty cycle comparison before final conversion operations. This preliminary action characterizes the conversion time under current PVT conditions and layout parasitics, allowing the system to establish appropriate timing margins that adapt to the specific operating conditions, thereby reducing timing margin uncertainty.
Solution Approach 2:
The patent changes the parameter being measured from absolute conversion time to duty cycle ratio, which is less sensitive to PVT variations and layout parasitics. By comparing the duty cycle of the feedback signal with a reference signal, the system extracts timing information that is normalized and more predictable, reducing timing margin uncertainty while maintaining adaptability to PVT variations.
Data Source
AI summary
A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.