SAR ADC Clock Control With Adaptive Duty Cycle Timing
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Solution Overview
Problem
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) face challenges due to the need for high-speed and unbalanced clocks with fixed duty cycles, which increase costs and prevent optimal operation, as the duty cycle cannot be fine-tuned adaptively.
Innovation Solution
A method and apparatus for controlling SAR ADCs by using a clock generator to control the termination and initiation timings of sampling and comparing phases with a variable duty cycle, allowing adaptive fine-tuning of the sampling clock's duty cycle based on the completion of tasks, enabling optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast clock with much higher rate than conversion clock is used, then sampling speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the sampling clock generation function into the existing conversion clock system by using edges of the conversion clock to control both sampling phase termination and next sampling phase initiation, eliminating the need for a separate fast clock generator and reducing overall system complexity
Solution Approach 2:
The conversion clock serves multiple functions: it controls the conversion rate, provides timing references for sampling phases, and triggers phase transitions. This multi-functionality eliminates the need for dedicated fast clocks while maintaining proper sampling speed through adaptive phase control
2Duration of action of moving object
If an unbalanced clock with fixed duty cycle (20%, 25%, or 40%) is used, then sampling phase duration is extended, but adaptability deteriorates because duty cycle cannot be fine-tuned
Solution Approach 1:
The patent implements dynamic duty cycle adjustment by using the completion signal of the last comparing task to adaptively control the sampling phase duration. The sampling clock's duty cycle is no longer fixed but dynamically tuned based on the actual conversion requirements, allowing optimal operation under varying conditions
Solution Approach 2:
The system uses feedback from the comparing phase completion status to adjust the sampling phase timing. The completion signal of the last comparing task feeds back to control the sampling clock generation, enabling automatic fine-tuning of the duty cycle without external intervention
3Duration of action of moving object
If fixed duty cycle unbalanced clock is used, then sampling time is increased, but optimal operation is prevented due to inability to fine-tune duty cycle
Solution Approach 1:
The sampling clock duty cycle is made dynamic and adaptive, automatically adjusting based on the completion status of comparing tasks. This allows the system to maximize sampling time when needed while maintaining optimal conversion efficiency under different operating conditions, preventing the fixed compromise of traditional designs
Data Source
AI summary
A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.