SAR ADC Reference DAC with Dynamic Element Matching

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Solution Overview

Problem

SAR-based ADCs face challenges with weight mismatch leading to static nonlinearity, harmonic distortion, and limited conversion speed due to sequential decisioning nature, which are exacerbated in reference ADCs requiring stringent linearity.

Innovation Solution

Implement a low-complexity dynamic element matching (DEM) technique using a cyclic shift register to randomly associate unit cells with decision bits in a SAR ADC, minimizing weight mismatch and harmonic distortion without increasing circuit complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a SAR ADC uses fixed unit cell weighting, then the circuit complexity is low, but weight mismatch causes static nonlinearity and harmonic distortion

Engineering Contradiction:
ImprovelinearityVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies dynamic element matching by making the unit cell-to-bit association dynamic rather than fixed. A random number generator continuously generates random associations between unit cells and decision bits, changing the weighting configuration over time. This dynamic approach converts static weight mismatch errors into random noise, improving linearity without requiring precise manufacturing of each unit cell's weight.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of unit cell association from fixed to randomly varying. By continuously changing which unit cells are associated with which decision bits through random number generation, the system transforms deterministic weight mismatch into stochastic noise, thereby improving spurious-free dynamic range and linearity performance.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If a SAR ADC uses sequential decisioning, then the circuit complexity is low, but the conversion speed is limited

Engineering Contradiction:
Improveconversion speedVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary randomization of unit cell associations before the conversion process begins. A random number generator pre-generates the association pattern, and this pattern is then used throughout the conversion. This preliminary action allows the sequential decisioning process to proceed efficiently while benefiting from the linearity improvements of dynamic element matching, without adding significant complexity to the critical conversion path.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If a reference ADC is designed with high linearity requirements, then the measurement precision is improved, but the power consumption increases

Engineering Contradiction:
ImprovelinearityVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent uses inexpensive random number generation to achieve linearity improvement instead of using expensive precision analog components. The randomization approach requires only simple digital logic and capacitors, avoiding the need for precisely matched analog weights that would consume more power. This disposable-like approach to weight matching (where precision is achieved through randomness rather than precision manufacturing) significantly reduces power consumption in the reference ADC.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20250317150A1Successive Approximation Register-Based Reference Analog-to-Digital Converter with Low-Complexity Dynamic Element Matching
Publication Date: 2025.10.09 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US20250317150A1 patent drawing
  • US20250317150A1 patent drawing
  • US20250317150A1 patent drawing

AI summary

A switched-element digital-to-analog converter (DAC) circuit for use, for example, in a successive-approximation register, SAR, analog-to-digital converter, ADC. The DAC circuit comprises a pool of unary circuit elements (410), each having a common nominal weighting value, and switching (420) and multiplexer (430) arrangements configured so that each unary circuit element (410) in the pool can be independently associated with any one of two or more bits of the switched-element DAC.