Single-Ended SAR ADC With Dynamic Reference for Extra Resolution
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Solution Overview
Problem
Existing single-ended SAR ADCs face challenges in resolving the Most Significant Bit (MSB) without additional hardware, especially when using bottom-plate sampling, leading to inefficiencies in area, power consumption, and precision due to the need for dedicated capacitors and potential gain errors.
Innovation Solution
A single-ended SAR ADC achieves (N+1) bits of resolution using an N-bit DAC array and top capacitor plate sampling, with a dynamic comparator reference that adjusts during the first bit cycle, avoiding dead zones and discontinuities by calibrating the DAC reference to compensate for parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bottom-plate sampling is used in single-ended SAR ADC, then the ADC can operate with single-ended topology, but the MSB resolution requires dedicated capacitors increasing area and power consumption
Solution Approach 1:
The patent merges the MSB resolution function with the existing bottom-plate sampling capacitors by dynamically switching the reference voltage applied to these capacitors. Instead of using dedicated MSB capacitors, the same capacitors serve dual purposes: sampling the input signal and resolving the MSB through dynamic reference voltage switching between Vref and ground.
Solution Approach 2:
The patent introduces dynamic switching of the reference voltage applied to the bottom-plate sampling capacitors during the conversion process. The reference voltage is dynamically changed from Vref to ground based on the MSB decision, enabling the same hardware to adaptively resolve the MSB without requiring dedicated static capacitors.
2Measurement precision
If dedicated capacitors are used for MSB resolution, then MSB can be resolved accurately, but power consumption increases
Solution Approach 1:
The patent makes the bottom-plate sampling capacitors multi-functional by using them for both input signal sampling and MSB resolution. The same capacitors that perform the primary sampling function are dynamically reconfigured to resolve the MSB, eliminating the need for separate dedicated MSB capacitors and reducing overall power consumption.
Solution Approach 2:
The patent temporarily discards the standard bottom-plate sampling operation during the MSB resolution phase by switching the reference voltage to ground, allowing the capacitors to be used for MSB determination. After MSB resolution, the capacitors are recovered and returned to their normal sampling function, maximizing hardware utilization.
3Device complexity
If dynamic reference voltage switching is used for MSB resolution, then hardware requirements are reduced, but gain errors may occur due to parasitic capacitance
Solution Approach 1:
The patent introduces a calibration process that measures the actual capacitance values of the bottom-plate sampling capacitors and uses this feedback information to adjust the reference voltage levels. By measuring the parasitic capacitance effects during calibration and compensating for them in the conversion algorithm, the system maintains high gain accuracy despite the dynamic reference voltage switching.
Solution Approach 2:
The patent dynamically changes the reference voltage parameter applied to the bottom-plate sampling capacitors during conversion and during calibration. By adjusting the reference voltage levels based on measured parasitic capacitance values, the system compensates for gain errors and maintains measurement precision while using the simplified dynamic topology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces hardware requirements, energy consumption, and gain errors while maintaining precision by dynamically setting the comparator reference, enabling efficient MSB resolution in single-ended implementations.
Implementation Method 1
the input voltage signal is sampled on the top plate of a capacitor during a sampling phase
Implementation Method 2
a voltage level on the top plate of the capacitor is compared to a reference voltage using a comparator
Data Source
AI summary
A single-ended successive approximation register (SAR) digital-to-analog converter (ADC) includes, in part, an array of N capacitors each having a first plate coupled to a first node. A second plate of each of the N capacitors is coupled to an associated one of N different switches configured to connect the second plate of the capacitor to a ground voltage or a reference voltage. The SAR ADC also includes a comparator having a first input receiving the voltage of the first node, and a second input that receives the reference voltage if the voltage at the first node during a first phase is smaller than the reference voltage. The second input to the comparator receives twice the reference voltage if the voltage at the first node during the first phase is greater than the reference voltage.