SAR ADC Embedded IIR Filtering for Blocking Signal Rejection
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Solution Overview
Problem
Wireless local area network (WLAN) wake-up radios face challenges in reducing power consumption and circuit size due to the presence of blocking signals, which existing technologies address inadequately using discrete filters that increase cost and die area.
Innovation Solution
Implementation of a successive approximation register (SAR) analog-to-digital converter (ADC) with an embedded infinite impulse response (IIR) filter that attenuates blocking signals using digital sample feedback to a capacitive digital-to-analog converter (CDAC), eliminating the need for additional filters and reducing die area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but die area and circuit size increase
Solution Approach 1:
The patent combines the filtering function with the existing SAR ADC structure by incorporating an infinite impulse response (IIR) filter directly into the analog-to-digital conversion process. The filter is implemented using the existing capacitive digital-to-analog converter (CDAC) and feedback paths within the SAR ADC, merging two functions (ADC and filtering) into a single integrated circuit block, thereby eliminating the need for separate discrete filters and reducing die area
Solution Approach 2:
The SAR ADC structure is designed to perform multiple functions: analog-to-digital conversion and signal filtering. The capacitive digital-to-analog converter (CDAC) and feedback mechanism are utilized not only for the standard SAR ADC operation but also to implement the IIR filter function, allowing a single circuit to serve dual purposes and reducing overall circuit complexity and area
2Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but power consumption increases
Solution Approach 1:
The filtering operation is merged with the ADC conversion process, so that the same circuit components perform both filtering and analog-to-digital conversion. The IIR filter is implemented using the existing CDAC and feedback paths, eliminating the need for separate filter circuitry that would consume additional power. This integration ensures that filtering is achieved without the extra power overhead of discrete filters
3Object-affected harmful factors
If discrete filters are used to attenuate blocking signals, then signal filtering performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the filtering function with the ADC structure by utilizing the existing capacitive digital-to-analog converter (CDAC) and feedback paths. The IIR filter is implemented within the same circuit blocks that perform analog-to-digital conversion, combining two functions into one integrated structure and reducing overall device complexity compared to using separate discrete filters
Solution Approach 2:
The SAR ADC structure is designed to perform multiple functions including analog-to-digital conversion and signal filtering. The same circuit components (CDAC, feedback paths, switches) are used for both ADC operation and IIR filtering, reducing the total number of components and simplifying the overall device architecture
Data Source
AI summary
An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.