Charge Redistribution SAR ADC for Comparator Error Compensation
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Solution Overview
Problem
High-resolution analog to digital (A/D) converters face challenges in linearity and accuracy due to slow or inaccurate comparators, leading to compromised performance and increased power consumption.
Innovation Solution
A charge redistribution successive approximation A/D converter circuit that uses a capacitor array and an amplifier, with a control unit to sample the input voltage and perform multiple conversion steps, achieving accurate digital output through weighted sum of conversion results while maintaining constant closed-loop bandwidth and settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional switched capacitor successive approximation A/D converters are used, then the conversion process is simple, but linearity and accuracy are compromised due to slow or inaccurate comparators
Solution Approach 1:
The A/D conversion process is divided into multiple conversion cycles, with each cycle handling a portion of the bits. The capacitor array is segmented into groups that are selectively coupled to different voltage sources across cycles. This segmentation allows the use of simpler, lower-power comparators in each cycle while achieving high overall resolution through the cumulative effect of multiple conversion steps.
Solution Approach 2:
The capacitor array performs preliminary charge storage during a sampling phase before conversion begins. The capacitors are pre-charged to the input voltage level, and then selectively redistributed during conversion cycles. This preliminary action allows the comparators to work with smaller voltage swings and reduces their complexity requirements while maintaining accuracy.
2Measurement precision
If high-resolution A/D conversion is achieved through multiple conversion cycles, then accuracy improves, but errors may accumulate across cycles
Solution Approach 1:
The circuit employs feedback by coupling certain capacitor groups to the output of the amplifier (which represents the conversion result) in subsequent conversion cycles. This feedback mechanism allows the circuit to compensate for errors by adjusting the charge distribution based on previous conversion results, preventing error accumulation and maintaining linearity across multiple conversion cycles.
Solution Approach 2:
The circuit discards the accumulated charge on capacitor groups after each conversion cycle and recovers it by re-coupling to the input voltage or reference voltages in the next sampling phase. This periodic discarding and recovering resets the charge state, preventing error accumulation while maintaining the ability to perform high-resolution conversions across multiple cycles.
3Measurement precision
If comparators are made more accurate to improve linearity, then conversion accuracy improves, but power consumption increases
Solution Approach 1:
The comparison process is segmented into multiple conversion cycles, with each cycle handling a subset of bits. This allows the use of simpler, lower-power comparators in each cycle rather than requiring a single high-power comparator to handle all bits at once. The total conversion accuracy is achieved through the cumulative effect of multiple low-power comparison steps.
Solution Approach 2:
The conversion process uses periodic action by alternating between sampling phases and multiple conversion cycles. During each conversion cycle, comparators perform their function with reduced complexity requirements, then the circuit transitions to the next phase. This periodic operation allows comparators to be simpler and consume less power while still achieving high overall conversion accuracy through the repeated conversion cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances A/D conversion accuracy and reduces power consumption by compensating for comparator inaccuracies and errors, ensuring reliable high-resolution conversions without accumulation of errors across cycles.
Implementation Method 1
A charge redistribution successive approximation A/D converter circuit that uses a capacitor array and an amplifier
Data Source
AI summary
In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.