SAR ADC Capacitor Weighting for Dynamic Error Tolerance

The patent changes the capacitor capacitance values from a power-of-two sequence (C0, 2C0, 4C0, ...) to a geometric sequence with ratio α where 1 < α < 2 (C0, αC0, α²C0, ...). This parameter change creates a 'gray area' tolerance that allows correction of incorrect bit resolutions. Specifically, when an incorrect resolution occurs, the remaining capacitors in the geometric sequence can compensate for the error because their weights are not strictly hierarchical like in the power-of-two case, enabling the ADC to tolerate and correct dynamic errors without requiring additional capacitors or complex calibration circuits.

The geometric sequence capacitor configuration is self-calibrating in nature. The specific ratio α (where 1 < α < 2) inherently provides the tolerance needed for error correction during the normal conversion process. When a bit resolution error occurs, the remaining capacitors automatically compensate for the error through their geometric weighting, eliminating the need for separate calibration circuits, additional capacitors, or elaborate digital correction logic. The system corrects its own errors through the mathematical properties of the geometric sequence.

By changing the capacitor weights to a geometric sequence with ratio α (1 < α < 2), the patent creates a tolerance buffer that allows the comparator to make correct decisions even when settling is incomplete. The geometric weighting ensures that the voltage contribution from remaining capacitors can compensate for errors introduced by incomplete settling of earlier capacitors. This allows the ADC to operate at higher speeds where settling time is limited, while maintaining accuracy that would normally require slower operation in conventional power-of-two designs.