SAR ADC Factoring with Background Clock Calibration for PVT Drift
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Solution Overview
Problem
Successive approximation register (SAR) analog to digital converters (ADCs) face limitations due to noise from comparators and mismatched DAC capacitors, leading to bandwidth harmonics, reduced effective number of bits, and increased nonlinearity, which are exacerbated by process, voltage, and temperature variations, resulting in power hungry and complex systems.
Innovation Solution
The implementation of a SAR ADC system with a factoring circuit and background clock calibration, which includes an oscillator calibration circuit and a fast clock calibration circuit, performs multiple conversions to average noise, and uses digital calibration to adjust sampling and conversion clocks, reducing sensitivity to PVT variations without increasing complexity or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC uses trimming of DAC capacitor or complicated on-chip calibration circuits to achieve high resolution, then measurement precision is improved, but device complexity and chip area increase significantly
Solution Approach 1:
The patent extracts the calibration function from complex on-chip circuits and relocates it to post-processing in the software environment. The ADC hardware is simplified to basic SAR ADC functionality, while calibration data is collected and processed externally, eliminating the need for complicated on-chip calibration circuits and capacitor trimming mechanisms.
Solution Approach 2:
The patent introduces an intermediary calibration process that bridges the ADC hardware and the controller/software. A calibration mode is implemented that allows the ADC to operate in a special state where calibration data can be collected and transferred to the controller for post-processing, serving as an intermediary between hardware conversion and software-based calibration.
2Device complexity
If post-processing calibration phase is performed in software environment, then device complexity is reduced, but measurement precision is limited versus PVT variations
Solution Approach 1:
The patent implements preliminary calibration actions by collecting calibration data during specific calibration modes before normal operation. The ADC is configured to gather calibration information that captures PVT variation characteristics, which are then used in post-processing to create correction data that compensates for PVT variations during actual conversions.
Solution Approach 2:
The patent changes the operational parameters of the ADC by implementing a calibration mode that modifies the conversion process to collect calibration data. The ADC switches between normal conversion mode and calibration mode, where in calibration mode it collects data under controlled conditions that allow characterization of PVT variations, which are then used to adjust conversion results.
3Measurement precision
If on-chip calibration circuits are implemented to mitigate comparator noise and DAC capacitor mismatch, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent extracts the calibration functionality from power-consuming on-chip circuits and relocates it to the software environment. The ADC hardware is reduced to essential components only, eliminating dedicated calibration circuits that would consume power. Calibration is performed using the ADC's existing resources under software control, with processing done externally where no additional hardware power is required.
Solution Approach 2:
The patent implements a self-service calibration approach where the ADC uses its own internal resources (DAC, comparator, conversion logic) to generate calibration data during calibration modes. No external calibration hardware or additional power-consuming calibration circuits are needed, as the ADC calibrates itself by collecting data in special modes and transferring calibration information to the controller for processing.
Data Source
AI summary
Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.