SAR ADC c-2c Ladder DAC Layout for Faster MSB Conversion
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Solution Overview
Problem
Conventional Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) face challenges in maintaining optimal operating time for resolution and stability due to increased response time and large capacitor ratios, which complicate integration and increase circuit complexity as resolution increases.
Innovation Solution
The proposed SAR ADC incorporates a Sample-and-Hold Amplifier, a comparator, an SAR logic circuit, and a c-2c ladder type Digital-to-Analog Converter (DAC) with a simplified circuit configuration, reducing the phase difference between the start signal and the digital signal of the Most Significant Bit (MSB) to one bit, and utilizing smaller capacitors to minimize area and noise, thereby optimizing operating time and reducing integration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary weighted capacitors are used in the DAC to achieve high linearity and low-power design, then the linearity and power efficiency are improved, but as resolution is increased, the ratio of the largest capacitor to the smallest capacitor is abruptly increased, requiring many more capacitors for matching, which increases the total area of the DAC and deteriorates integration
Solution Approach 1:
The patent divides the binary-weighted capacitor array into two separate capacitor arrays: a first capacitor array for the most significant bit (MSB) and a second capacitor array for the remaining bits. This segmentation allows each array to be optimized independently, reducing the overall capacitor size ratio and improving integrability while maintaining high linearity performance.
2Ease of operation
If the conventional SAR ADC includes a start stage and an inverting gate for resetting the SR flip-flop, then the digital signal generation is achieved, but the digital signal of the MSB has a 2-phase difference with the start signal, which increases the operating time and makes it difficult to operate the SAR during an optimized time for resolution
Solution Approach 1:
The patent removes the inverting gate from the conventional SAR ADC structure. By eliminating this component, the phase difference between the start signal and the MSB digital signal is reduced from 2 phases to 1 phase, thereby reducing the operating time and allowing the SAR to operate during the optimized time for resolution.
3Manufacturing precision
If the capacitor size is increased to maintain matching characteristics, then the matching precision is improved, but the total area of the DAC is increased, thereby deteriorating integration and complicating the circuit
Solution Approach 1:
The patent applies different capacitor configurations to different parts of the DAC: the first capacitor array uses larger capacitors optimized for MSB matching, while the second capacitor array uses smaller capacitors for the remaining bits. This local optimization maintains matching characteristics where needed while reducing overall circuit complexity and area.
Data Source
AI summary
A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.