SAR-ADC Feed-Forward Equalization for Inter-Symbol Interference
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Solution Overview
Problem
High-frequency components of signals transferred through communication channels in electronic devices weaken due to factors like skin effect and dielectric loss, leading to signal distortion and reduced quality, especially at high speeds.
Innovation Solution
A successive approximation register analog-to-digital converter (SAR-ADC) is configured to perform the function of a feed forward equalizer without a separate feed forward equalizer by using capacitive digital-to-analog converters (C-DACs) with multiple taps that sample input voltages at different points in time, applying varying weights to simulate the FFE effect, thereby reducing circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate feed forward equalizer is used to compensate signal distortion, then signal quality is improved, but chip area and power consumption increase
Solution Approach 1:
The patent combines the feed forward equalizer function with the SAR-ADC by integrating multiple taps into the ADC structure. The taps sample the analog signal at different time points and weights are applied during the conversion process, merging two separate functions (FFE and ADC) into a single integrated circuit, thereby reducing chip area while maintaining signal quality compensation
Solution Approach 2:
The SAR-ADC is designed to perform multiple functions: it acts as both an analog-to-digital converter and a feed forward equalizer. The multi-tap structure with selectable weights enables the ADC to simultaneously execute conversion and equalization tasks, making the device universal and eliminating the need for a separate FFE circuit
2Reliability
If a separate feed forward equalizer is used to compensate signal distortion, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent combines the feed forward equalizer function with the SAR-ADC by integrating multiple taps into the ADC structure. The taps sample the analog signal at different time points and weights are applied during the conversion process, merging two separate functions (FFE and ADC) into a single integrated circuit, thereby reducing chip area while maintaining signal quality compensation
Solution Approach 2:
The SAR-ADC is designed to perform multiple functions: it acts as both an analog-to-digital converter and a feed forward equalizer. The multi-tap structure with selectable weights enables the ADC to simultaneously execute conversion and equalization tasks, making the device universal and eliminating the need for a separate FFE circuit
3Reliability
If multiple taps sample at different time points with varying weights, then inter-symbol interference compensation is improved, but circuit complexity increases
Solution Approach 1:
The equalization function is segmented into multiple taps, where each tap samples the analog signal at a different time point and applies a specific weight. This segmentation allows independent optimization of each tap's sampling timing and weighting, simplifying the overall design by breaking down the complex equalization task into manageable discrete units
Solution Approach 2:
The circuit incorporates dynamic elements including switched capacitor networks and control logic that adjust tap weights and sampling timings based on signal conditions. The SAR-ADC dynamically selects which taps to activate and their respective weights during the conversion process, enabling adaptive equalization without requiring a permanently complex circuit structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SAR-ADC effectively compensates for signal distortion caused by inter-symbol interference, maintaining signal quality and reducing circuit size and power consumption without the need for a separate FFE.
Implementation Method 1
a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage
Implementation Method 2
a first analog-to-digital converter that includes a first plurality of capacitors for sampling the first input voltage and a second plurality of capacitors for sampling the second input voltage
Data Source
AI summary
The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.