Two-Stage SAR ADC Residue Amplifier With Feedback Gain Control
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Solution Overview
Problem
Conventional single-stage SAR ADCs face challenges in achieving high accuracy due to exponential growth in total capacitance, reduced residual voltage, and limitations from capacitance mismatch and comparator noise, while multi-stage SAR ADCs are hindered by gain error and offset voltage of residue amplifiers.
Innovation Solution
A two-stage SAR ADC architecture utilizing a difference and differential amplifier is introduced, incorporating a first-stage sub-ADC, a difference and differential amplifier, and a second-stage sub-ADC, with a calibrating circuit for offset voltage calibration and a digital logic control circuit to manage the sub-ADCs, forming a negative feedback loop with transconductance amplifiers and resistors to regulate gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-stage SAR ADC is used to achieve high accuracy, then conversion precision is improved, but total capacitance shows exponential growth and residual voltage reduces to sub-millivolt level
Solution Approach 1:
The patent divides the single-stage high-precision ADC into multiple stages, each handling a portion of the conversion process. The first stage performs coarse conversion with smaller capacitance, while subsequent stages refine the result, avoiding the exponential capacitance growth required for single-stage high-precision conversion.
Solution Approach 2:
The patent introduces a temporal dimension by using multi-stage sequential conversion instead of single-stage simultaneous conversion. The conversion process is unfolded across multiple time stages, allowing each stage to operate with manageable capacitance values while achieving cumulative high precision.
2Measurement precision
If a single-stage SAR ADC is used to achieve high accuracy, then conversion precision is improved, but resolution is greatly affected by capacitance mismatch and comparator noise
Solution Approach 1:
By segmenting the conversion into multiple stages, each stage operates with reduced capacitance values and smaller voltage swings, thereby reducing the impact of capacitance mismatch and comparator noise on the overall conversion accuracy.
Solution Approach 2:
The first stage performs preliminary coarse conversion, removing the most significant bits and reducing the residual voltage to a manageable level before passing it to subsequent stages. This preliminary action prevents large voltage differences from amplifying noise and mismatch effects in later stages.
3Measurement precision
If a multi-stage SAR ADC is used to achieve higher accuracy, then conversion accuracy is improved, but accuracy is limited by gain error and offset voltage of residue amplifier
Solution Approach 1:
The patent implements a feedback mechanism where the output of each stage is fed back to correct errors before being passed to the next stage. The residue amplifier's gain error and offset voltage are compensated through feedback control, preventing these errors from accumulating and limiting the overall conversion accuracy.
Solution Approach 2:
Offset calibration is performed preliminarily before the main conversion process. The calibrating circuit measures and compensates for the residue amplifier's offset voltage in advance, ensuring that subsequent conversions are not degraded by this systematic error.
4Power
If conventional residue amplifier structure is used in multi-stage SAR ADC, then amplification function is achieved, but offset voltage calibration is required and gain stability is affected
Solution Approach 1:
The patent combines the offset calibration function and gain control function into an integrated residue amplifier structure. The same amplifier circuit performs both amplification and self-calibration, eliminating the need for separate calibration circuits and reducing overall device complexity.
Solution Approach 2:
The residue amplifier is designed to perform self-calibration by using its own output to generate calibration signals. The amplifier automatically adjusts its offset and gain parameters without requiring external calibration equipment, reducing system complexity and improving manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gain error, improves accuracy, reduces size and cost, avoids charge leakage, and achieves stable high conversion accuracy compared to conventional structures.
Implementation Method 1
the difference and differential amplifier includes a transconductance amplifier GM1, a transconductance amplifier GM2, a resistance load R, and proportional resistors R1 and R2
Implementation Method 2
passing the current signal IiP through the resistance load R and outputting a voltage signal VO
Implementation Method 3
by taking the VO divided by the proportional resistors R1 and R2 as an input of the transconductance amplifier GM2
Implementation Method 4
the transconductance amplifier GM1, the resistance load R, and the transconductance amplifier GM2 form a negative feedback loop
Data Source
AI summary
Disclosed is a two-stage successive approximation register analog to digital converter based on a difference and differential amplifier, including a first-stage sub-ADC, a difference and differential amplifier, and a second-stage sub-ADC connected in sequence. The first-stage sub-ADC and the second-stage sub-ADC each include capacitor arrays and comparators. The difference and differential amplifier includes a transconductance amplifier GM1, a transconductance amplifier GM2, a resistance load R, and proportional resistors R1 and R2. The transconductance amplifier GM1, the resistance load R, and the transconductance amplifier GM2 form a negative feedback loop. The disclosure adjusts the gain of the amplifiers through the proportional resistors R1 and R2, so that higher conversion accuracy can be achieved.