SAR ADC Feedback Gating to Prevent Forbidden-State Bit Errors
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in operating at high speeds due to the occurrence of probabilistic errors, specifically the forbidden state where the SAR logic circuitry writes the same logical value to the conversion result twice, leading to erroneous bit values and subsequent bits being affected.
Innovation Solution
The implementation of digital feedback logic in the SAR ADC, where the positive output of the comparator is gated by opposite polarity information from the negative output, and vice versa, using NAND gates and asynchronous clock generation to prevent the forbidden state by ensuring each bit trial's results are correctly written without overlap of shift register clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SAR ADC operates at high speeds, then conversion speed is improved, but probabilistic errors occur due to forbidden state
Solution Approach 1:
The patent implements a feedback mechanism where the output of the comparator is fed back to the SAR logic circuitry through digital feedback paths. This feedback allows the circuit to detect when a forbidden state occurs (when both positive and negative outputs are valid simultaneously) and prevents erroneous bit writing by using the feedback signal to control the timing and validity of comparison results, thereby eliminating probabilistic errors while maintaining high conversion speed.
Solution Approach 2:
The patent introduces digital feedback logic as an intermediary between the comparator and the SAR logic circuitry. This intermediary layer processes the comparator outputs and generates control signals that mediate the interaction between comparison results and bit writing operations, preventing the direct coupling that causes forbidden states and enabling reliable high-speed operation.
2Reliability
If digital feedback logic is implemented, then bit error probability is reduced, but device complexity increases
Solution Approach 1:
The patent segments the feedback mechanism into distinct digital feedback paths corresponding to different comparator outputs (positive and negative outputs). Each feedback path is independently controlled and routed to specific logic gates within the SAR circuitry. This segmentation allows the feedback logic to be integrated systematically without creating a monolithic complex structure, making the design more manageable and implementable.
3Reliability
If gating logic is used to prevent forbidden state, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic gating control where the digital feedback signals periodically enable or disable the gating logic based on the timing of comparison operations. The gating is activated only when needed (during critical comparison windows) and deactivated otherwise, creating a periodic action pattern. This approach allows the gating logic to prevent forbidden states during critical periods while consuming minimal power during non-critical periods, balancing reliability improvement with power efficiency.
Data Source
AI summary
Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.