SAR ADC Feedback Loop for Capacitor Mismatch Tolerance
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Solution Overview
Problem
Conventional image sensors with parallel analog-to-digital converters face issues due to capacitor mismatches and non-linearities, leading to signal offsets and limited common-mode range, resulting in higher power consumption and lower operating speed.
Innovation Solution
The implementation of a successive approximation register (SAR) ADC circuit with input sampling capacitors that are embedded in the feedback loop, eliminating charge sharing between capacitors and allowing the ADC to operate beyond its supply voltage range, thereby improving signal-to-noise ratio and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If charge sharing is used between input sampling capacitors and binary weighted capacitors in a SAR ADC, then the ADC can convert analog signals to digital signals, but capacitor mismatches and non-linearities cause signal offsets and reduce measurement precision
Solution Approach 1:
The patent divides the ADC architecture into independent parallel channels, each with its own sampling capacitor and SAR ADC unit. This segmentation isolates capacitor mismatches to individual channels, preventing them from affecting the entire system. Each channel processes signals independently, so mismatches in one channel do not propagate to others, thereby maintaining measurement precision despite capacitor variations.
Solution Approach 2:
The patent implements a feedback mechanism where the output of each SAR ADC is fed back to adjust the sampling capacitor values dynamically. This feedback loop compensates for capacitor mismatches and non-linearities by adjusting the sampling capacitance in real-time, ensuring that signal precision is maintained even when physical capacitor values deviate from design specifications.
2Adaptability or versatility
If the ADC operates with a common-mode range limited by supply voltage, then the circuit design is simplified, but the ADC cannot handle high common-mode voltage signals without attenuation
Solution Approach 1:
The patent extends the common-mode voltage handling capability by introducing a voltage translation dimension. The ADC circuit incorporates level-shifting mechanisms that allow it to process signals with common-mode voltages exceeding the supply voltage range. This is achieved by adding a voltage offset dimension to the signal processing path, enabling the ADC to accept high common-mode signals and translate them into the acceptable input range for conversion.
Solution Approach 2:
The patent introduces intermediary circuitry between the input sampling stage and the SAR ADC core. This intermediary layer includes voltage translation circuits and level shifters that mediate between high common-mode voltage signals and the ADC's limited input range. The intermediary circuits perform the voltage level conversion, allowing the main ADC circuit to remain relatively simple while still handling high common-mode voltages through this intermediate translation stage.
3Productivity
If parallel ADCs are used to increase throughput, then more input sampling capacitors are required, but capacitor mismatches and parasitic capacitances increase leading to more signal offsets
Solution Approach 1:
The patent segments the parallel ADC system into independent processing channels, where each channel has its own dedicated sampling capacitor and SAR ADC unit. This segmentation strategy allows the system to achieve high throughput through parallel processing while isolating capacitor mismatches and parasitic effects to individual channels. The independent architecture ensures that mismatches in one channel do not affect other channels, maintaining signal offset accuracy despite the large number of capacitors required for high throughput.
Solution Approach 2:
The patent dynamically adjusts capacitor parameters including sampling capacitance values and switching timing across different parallel channels. By varying these parameters, the system optimizes the trade-off between throughput and precision for each channel. The parameter changes include adjusting the sampling capacitor size and switching时序 to compensate for parasitic capacitances and mismatches, thereby maintaining signal offset accuracy while achieving high overall throughput through the parallel architecture.
Data Source
AI summary
An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.