SAR ADC Feedback Circuit for Mixer-Free Multi-Band Reception

The patent combines multiple PLL functions into a single PLL by using a variable reference frequency input. Instead of requiring separate PLLs for different frequencies, the system feeds back filtered differential signals to the PLL input, allowing the same PLL to generate appropriate clock signals for various frequency bands through frequency division and filtering operations.

The PLL circuit is designed to perform multiple functions: it generates clock signals for different frequency bands, performs frequency division, and works in conjunction with the bandpass filter to select appropriate frequencies. This multi-functional design eliminates the need for separate PLL instances for each frequency band.

The patent merges multiple PLL circuits into a single PLL by implementing a feedback mechanism where differential signals are bandpass filtered and fed back to the PLL input. This consolidation reduces the number of PLL circuits from multiple to one, thereby reducing device complexity while maintaining multi-frequency support capability.

The system segments the frequency selection function into separate stages: the PLL generates a master clock signal, frequency division creates intermediate frequencies, and the bandpass filter selects the final desired frequency. This segmentation allows a single PLL to serve multiple frequency bands without requiring multiple PLL circuits.