SAR ADC Data Register With High-Speed Flip-Flop Switching
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Solution Overview
Problem
Conventional SAR ADCs require a large number of transistors and operate slowly due to the use of conventional D flip-flops in their data register units, limiting their speed and efficiency.
Innovation Solution
A high-speed flip-flop circuit with a simple structure is introduced, comprising PMOS and NMOS transistors, an inverter, and a logic gate, which reduces the number of transistors required and enhances operation speed by allowing faster capacitor switching based on comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional D flip-flops are used in data register units, then reliability is improved, but operation speed deteriorates and transistor count increases
Solution Approach 1:
The patent creates a simplified copy of the flip-flop functionality using basic logic gates (AND, OR, NOT) instead of conventional D flip-flops. This copy performs the same data storage and transfer function but with reduced complexity and faster operation, directly resolving the contradiction between reliability and speed.
Solution Approach 2:
The patent segments the flip-flop function into discrete logic gate operations (AND gate for data input, OR gate for output control, NOT gate for inversion) that can be executed faster than conventional flip-flop circuits. This segmentation enables faster operation while maintaining the essential functionality.
2Reliability
If conventional D flip-flops are used in data register units, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex conventional D flip-flop structures with a simplified copy using basic logic gates. This copy maintains the essential flip-flop functionality while significantly reducing transistor count and circuit complexity, directly addressing the contradiction between reliability and device complexity.
Solution Approach 2:
The patent extracts only the essential functionality needed for the data register operation, removing unnecessary components and complexity from conventional D flip-flops. By taking out only the critical data storage and transfer functions and implementing them with simpler logic gates, the design achieves lower complexity while maintaining reliability.
3Device complexity
If simpler flip-flop structures are used, then device complexity is reduced, but operation speed may deteriorate
Solution Approach 1:
The patent implements dynamic control of the logic gates using clock signals that coordinate the operation of AND, OR, and NOT gates. This dynamic timing control ensures that data flows through the simplified structure at the required speed, preventing operation speed deterioration despite the simpler structure.
Solution Approach 2:
The patent uses preliminary clock signal conditioning and gate enablement to prepare the simplified flip-flop structure for fast operation. By pre-synchronizing the logic gates with clock edges and ensuring they are ready to switch states, the design maintains high operation speed despite the reduced structural complexity.
Data Source
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AI summary
A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop (710); a second high-speed flip-flop (720); and a third logic gate (730), wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor (P1), a first NMOS transistor (N1), an inverter (620) and a logic gate (610). The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.