Two-Stage SAR ADC With Floating Capacitors for High-Range Sampling
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Solution Overview
Problem
Conventional successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in handling high input voltage ranges without degrading the signal-to-noise ratio (SNR), as they require dividing the input signal to fit within the comparator's voltage range, leading to decreased SNR and the need for high-voltage transistors.
Innovation Solution
The solution involves a first ADC stage with floating capacitors that sample the input voltage without initial division, using a secondary ADC stage to make initial bit decisions, allowing the capacitors to be coupled to reference signals based on these decisions, thereby maintaining the full charge and SNR during subsequent conversion steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the input signal is divided to fit within the comparator's voltage range, then the ADC can handle high input voltage ranges, but the signal-to-noise ratio (SNR) decreases
Solution Approach 1:
The ADC conversion process is segmented into two stages: a first ADC stage that samples the full input voltage range without division, and a second ADC stage that performs conventional conversion. The floating capacitors in the first stage hold the full-scale charge, avoiding SNR degradation while the second stage handles the actual conversion with proper voltage scaling.
Solution Approach 2:
Floating capacitors act as intermediaries that store the full-scale input voltage charge without requiring voltage division. These capacitors couple the input signal to the conversion process, allowing the full input range to be sampled while the conversion itself occurs at reduced voltage levels through the controlled coupling mechanism.
2Ease of operation
If conventional SAR ADC architecture is used, then the conversion process is straightforward, but high-voltage transistors are required and chip area increases
Solution Approach 1:
The ADC is divided into two functional stages with distinct roles: the first stage captures the full input voltage range using floating capacitors, while the second stage performs the actual successive approximation conversion. This segmentation allows each stage to be optimized independently, reducing the need for high-voltage transistors across the entire circuit.
Solution Approach 2:
The voltage parameters are changed through controlled coupling: the floating capacitors maintain full-scale voltage during sampling, then couple this charge to the second stage which operates at reduced voltage levels. This parameter transformation allows standard low-voltage transistors to be used in the majority of the circuit while still handling high input voltages.
3Reliability
If signal division is performed before conversion, then the comparator voltage range is satisfied, but conversion errors increase and calibration requirements increase
Solution Approach 1:
The floating capacitors perform preliminary sampling of the full input voltage range before the actual conversion process. By capturing the full-scale charge in advance and holding it on the floating capacitors, the system preserves the complete signal information without division-induced errors, then couples this pre-sampled charge to the conversion stage.
Solution Approach 2:
The floating capacitors serve as intermediary storage elements that decouple the input sampling from the conversion process. They hold the full-scale charge and control its coupling to the second stage, eliminating the need for signal division and associated errors while maintaining proper voltage levels for comparator operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high input voltage sampling without signal division, maintaining the SNR and reducing errors, with a simple error correction scheme to ensure convergence, and minimizing chip area and calibration requirements.
Implementation Method 1
sampling an input voltage on a first plurality of capacitors
Implementation Method 2
The sampled charge is redistributed stepwise among the capacitors of the CDAC
Data Source
AI summary
An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.