SAR ADC Gain Calibration Using Floating Capacitors
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Solution Overview
Problem
Successive-approximation analog-to-digital converters (ADCs) face challenges in efficiently converting high-voltage analog signals due to the need for high-voltage transistors, which increase circuit size and power consumption, and suffer from gain errors caused by capacitance mismatches.
Innovation Solution
The design incorporates a gain tuning capacitance to sequester a portion of the sampled input charge, using a charge-redistribution DAC and a reference voltage to approximate the input analog signal, while reducing the number of high-voltage transistors by separating input and conversion capacitances, and employing a programmable gain tuning circuit to adjust the gain and compensate for capacitance mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage transistors are used to convert high-voltage analog signals, then the conversion capability is improved, but circuit size and power consumption increase
Solution Approach 1:
The patent divides the capacitance function into separate components: input sampling capacitance and conversion capacitance. This segmentation allows each capacitance to be optimized independently, reducing the need for high-voltage transistors while maintaining high-voltage signal conversion capability. The input capacitance handles the high-voltage sampling, while the conversion capacitance operates at lower voltages during the conversion phase.
Solution Approach 2:
The patent extracts the high-voltage handling function from the transistor domain and transfers it to the capacitance domain. By using capacitors to store and transfer the sampled charge instead of using high-voltage transistors for the entire conversion process, the circuit avoids the size and power penalties associated with high-voltage transistor operation.
2Adaptability or versatility
If high-voltage transistors are used to convert high-voltage analog signals, then the conversion capability is improved, but power consumption increases
Solution Approach 1:
The conversion process is segmented into sampling phase and conversion phase. During sampling, the input capacitance captures the high-voltage signal. During conversion, the stored charge is redistributed to the conversion capacitance at lower voltage levels. This temporal segmentation allows low-voltage transistors to be used during the power-consuming conversion phase, reducing overall power consumption while maintaining high-voltage signal handling capability.
3Measurement precision
If capacitance values are increased to improve conversion accuracy, then measurement precision is improved, but capacitance mismatches increase
Solution Approach 1:
By separating the input sampling capacitance from the conversion capacitance, the patent allows each capacitance to be optimized for its specific function. The input capacitance can be sized for adequate signal capture, while the conversion capacitance can be precisely matched for accurate voltage division. This segmentation reduces the impact of manufacturing variations because the capacitances operate in different phases and don't need to be perfectly matched to each other.
Solution Approach 2:
The patent implements a self-calibration mechanism where the ADC automatically adjusts for capacitance mismatches during operation. The calibration circuit measures the actual capacitance values and applies correction factors to the conversion process, allowing the system to compensate for manufacturing variations without requiring extremely precise capacitance matching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces circuit size, increases speed, lowers power consumption, and improves resolution by accurately converting high-voltage signals with reduced capacitance mismatches, enhancing the overall performance of the successive-approximation ADC.
Implementation Method 1
an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion
Implementation Method 2
The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase
Implementation Method 3
a charge-redistribution DAC having a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion of the sampled input charge, a remaining portion of the sampled input charge stored on the input capacitance, and a reference voltage to provide an analog signal on the first node
Data Source
AI summary
A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.