SAR-ADC Gain Control in Direct Sampling Tuners
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Solution Overview
Problem
Existing direct sampling receivers face issues with thermal noise, intermodulation distortion, and circuit complexity due to traditional fine digital gain control methods, which limit their ability to handle a wide amplitude range of signals and lead to compression and further distortion.
Innovation Solution
A direct sampling tuner/receiver architecture incorporating a charge redistribution SAR-ADC with a variable gain control component, utilizing a capacitor array and switch configuration to provide accurate and predictable gain adjustment, reducing thermal noise and intermodulation distortion while maintaining signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fine digital gain control methods (switched gm stages, FET switched R-2R ladders) are used, then gain adjustment capability is provided, but thermal noise and intermodulation distortion increase
Solution Approach 1:
The patent extracts the gain control function from separate circuit stages and integrates it directly into the SAR-ADC capacitor array. By placing capacitors in parallel with the main capacitor array and controlling their connection through switches, the gain adjustment capability is embedded within the ADC structure itself, eliminating the need for separate gain control circuits that generate thermal noise and intermodulation distortion.
Solution Approach 2:
The patent merges the gain control function with the SAR-ADC capacitor array by integrating variable gain capacitors directly into the existing capacitor structure. This combination allows the ADC to perform both analog-to-digital conversion and gain adjustment in a single unified circuit, rather than requiring separate gain control stages that would add noise and distortion.
2Adaptability or versatility
If traditional fine digital gain control circuits are added, then gain control is achieved, but circuit complexity increases
Solution Approach 1:
The patent combines the gain control function with the SAR-ADC capacitor array, integrating multiple functions into a single circuit structure. The variable gain capacitors are placed in parallel with the main capacitor array and controlled by switches that are part of the existing ADC control logic, eliminating the need for separate gain control circuits and reducing overall system complexity.
Solution Approach 2:
The SAR-ADC capacitor array is designed to serve multiple functions: it performs the primary analog-to-digital conversion function while simultaneously providing gain control capability through the inclusion of variable gain capacitors. This multi-functionality reduces the need for additional dedicated circuits, thereby reducing overall circuit complexity.
3Device complexity
If fixed gain amplifier stage is used before ADC, then simple circuit structure is maintained, but output amplitude increases with input leading to compression and intermodulation distortion
Solution Approach 1:
The patent replaces the fixed gain amplifier stage with a dynamic gain control mechanism implemented through the SAR-ADC capacitor array. The variable gain capacitors can be dynamically adjusted based on the input signal amplitude, allowing the ADC to adapt its gain in real-time. This dynamic adjustment prevents output amplitude from increasing in sympathy with the input, thereby avoiding compression and intermodulation distortion while maintaining signal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables effective amplitude adjustment of incoming signals, allowing for enhanced post-processing and digital conversion without introducing additional noise or distortion, thereby improving the overall performance and reliability of direct sampling receivers.
Implementation Method 1
charge redistribution SAR-ADC architecture
Data Source
AI summary
A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.