Switched-Capacitor SAR ADC Gate Sequencing for Low-Power Switching

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Solution Overview

Problem

Conventional successive approximation register analog-to-digital converters (SAR ADCs) experience high power consumption due to short-circuit currents and voltage ripples caused by simultaneous switching of P-type and N-type MOSFETs during control signal transitions.

Innovation Solution

The SAR ADC incorporates a driving circuit with a P-type MOSFET and an N-type MOSFET, where the gate of the P-type MOSFET is not connected to the gate of the N-type MOSFET, and a control circuit with inverters to generate control signals that ensure the P-type MOSFET turns off before the N-type MOSFET turns on, preventing simultaneous switching and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the P-type MOSFET and N-type MOSFET are switched simultaneously during control signal transitions, then the switching operation is efficient and fast, but short-circuit currents and voltage ripples are generated causing high power consumption

Engineering Contradiction:

Improveswitching speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The control circuit generates control signals with staggered timing, where one MOSFET is turned off before the other is turned on. This preliminary sequencing prevents simultaneous conduction of both MOSFETs, eliminating short-circuit currents while maintaining efficient switching operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The control circuit acts as an intermediary between the digital logic and the MOSFET gates, introducing controlled delays through buffer stages. This intermediary function ensures that control signals are transmitted with appropriate timing separation, preventing direct simultaneous switching of both MOSFETs.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If the P-type MOSFET and N-type MOSFET are switched simultaneously, then the control signal transition is quick, but voltage ripples are caused affecting signal stability

Engineering Contradiction:

Improvecontrol signal transition timeVSAvoidvoltage stability

Core Design Contradiction:

Loss of timeVSStability of the object's composition

Solution Approach 1:

The control circuit pre-sequences the switching operations by generating control signals where one MOSFET turns off before the other turns on. This preliminary timing arrangement eliminates voltage ripples caused by simultaneous switching while maintaining quick transition times through optimized buffer design.

Inventive Principle:

Principle #10Preliminary action

3Loss of energy

If separate control signals are generated for P-type and N-type MOSFETs to prevent simultaneous switching, then power consumption is reduced, but the control circuit complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcontrol circuit complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The control circuit uses a universal buffer stage design that can be replicated for multiple MOSFET control applications. Each buffer stage performs the same function of signal inversion and timing delay, allowing the complex control function to be achieved through standardized, modular circuit elements rather than custom complex logic.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively eliminates short-circuit currents and voltage ripples, resulting in low power consumption and improved performance of the SAR ADC.

Implementation Method 1

The gate of the P-type MOSFET is not connected to the gate of the N-type MOSFET, and a control circuit with inverters to generate control signals that ensure the P-type MOSFET turns off before the N-type MOSFET turns on

Methodology Applied

Scientific EffectMOSFET switching control:

Implementation Method 2

The control signal G controls the terminal voltage of the capacitors in the switched-capacitor DAC 110 (i.e., controlling the bottom plate of the capacitors to be coupled to the reference voltage Vref1 or the reference voltage Vref2), so that the charges on the capacitors redistribute, leading to a change in the voltage at the inverting input or non-inverting input of the comparator 120

Methodology Applied

Scientific EffectCharge redistribution: Capacitance

Data Source

PatentUS10727856B2Successive approximation register analog-to-digital converter and control circuit thereof

Publication Date: 2020.07.28 REALTEK SEMICON CORP

AI summary

This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.