SAR ADC Harmonic-Rejection Mixing for Lower-Power Down-Conversion
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Solution Overview
Problem
Conventional radio frequency receivers face challenges with high ADC complexity, inefficient resource use, and high power consumption due to large bandwidth requirements in digital down-conversion, or high down-conversion complexity and power consumption in analog down-conversion using harmonic rejection mixers.
Innovation Solution
A successive approximation register (SAR) analog-to-digital converter (ADC) is integrated with harmonic rejection mixer functionality, utilizing a capacitor bank for dynamic scaling and mixing, allowing for efficient down-conversion and analog-to-digital conversion with reduced complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If down-conversion is performed in the digital domain, then the ADC can operate at lower frequencies, but the ADC requires relatively large bandwidth which entails high ADC complexity and high power consumption
Solution Approach 1:
The patent combines the down-conversion mixer functionality with the SAR ADC into a single integrated circuit block. The capacitor bank serves dual purposes: it performs the mixing operation by dynamically scaling the analog input signal with oscillator samples, and it simultaneously performs the analog-to-digital conversion. This merging eliminates the need for separate mixer and ADC circuits, reducing overall system complexity while maintaining the benefit of lower operating frequencies.
Solution Approach 2:
The SAR ADC is designed to perform multiple functions: it acts as both a mixer for down-conversion and an ADC for signal conversion. The capacitor bank dynamically scales the input signal based on oscillator samples (mixing function) while also performing the successive approximation conversion process. This multi-functionality allows the same hardware resources to handle both down-conversion and conversion tasks, reducing the need for dedicated hardware for each function.
2Speed
If down-conversion is performed in the digital domain, then the ADC can operate at lower frequencies, but this entails inefficient use of the ADC resources
Solution Approach 1:
The patent merges the mixing operation with the ADC conversion process in time and space. The capacitor bank performs dynamic scaling during the sampling phase of the SAR ADC operation, utilizing the same hardware resources that would otherwise be idle or underutilized during the conversion phases. This integration ensures that ADC resources are productively used throughout the entire operating cycle.
Solution Approach 2:
The mixing operation is performed continuously during the SAR ADC sampling phase, ensuring that the capacitor bank and associated circuitry are continuously engaged in useful work. Rather than having separate mixer and ADC operations that would require alternating activation, the system performs both functions simultaneously and continuously, maximizing resource utilization and productivity.
3Speed
If down-conversion is performed using a harmonic rejection mixer, then the down-conversion can be performed in the analog domain, but this entails high down-conversion complexity and high power consumption
Solution Approach 1:
The patent combines the harmonic rejection mixer functionality with the SAR ADC into a single integrated block, eliminating the need for a separate power-consuming mixer circuit. The mixing operation is performed using the capacitor bank and control logic already present in the SAR ADC, significantly reducing the additional power consumption that would result from adding a dedicated analog mixer.
Solution Approach 2:
The SAR ADC performs the down-conversion mixing operation using its own internal resources (capacitor bank, control logic, oscillator) without requiring external mixer circuitry. The system serves its own down-conversion needs through its existing components, eliminating the need for separate powered mixer hardware and reducing overall power consumption.
Data Source
AI summary
A successive approximation register analog-to-digital converter (SAR ADC) is disclosed, which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC comprises a capacitor bank for successively providing a plurality of signal levels based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC comprises controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal. In some embodiments, a respective selector of each capacitor of the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or the sample value of an opposed version of the analog input signal. The setting of the respective selectors corresponds to a digital representation of a scaling value (e.g., a sample value of an oscillator signal) for the dynamically scaled version of the sample value of the analog input signal. Corresponding method, receiver, and wireless communication device are also disclosed.