SAR ADC Capacitor Switching for Comparator Impedance Matching
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Solution Overview
Problem
Impedance mismatch between P-type and N-type MOSFET switches in conventional SAR ADCs leads to poor signal-to-noise and distortion ratio (SNDR) due to mismatched impedance values at the comparator's input terminals.
Innovation Solution
The SAR ADC employs a switch-capacitor DAC with capacitors having equal capacitance values, where the bottom plates of these capacitors are coupled to different reference voltages, and a control circuit manages the capacitors' activation and deactivation based on comparison results to improve impedance matching during the comparison and switching phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switch-capacitor DAC uses P-type and N-type MOSFET switches with different impedance values, then the circuit can be implemented with standard transistors, but the impedance mismatch causes errors and poor signal-to-noise and distortion ratio
Solution Approach 1:
The patent applies asymmetry by intentionally creating an imbalance in the capacitor array configuration. Specifically, it uses capacitor pairs where one capacitor is connected to the positive input terminal and the other to the negative input terminal, with deliberate impedance differences introduced through switch configurations. This asymmetric arrangement compensates for the inherent P-type and N-type MOSFET impedance mismatch, allowing the differential signals to balance out the transistor impedance differences and improve both reliability and measurement precision simultaneously
2Ease of manufacture
If the impedance values at comparator input terminals are mismatched, then the circuit implementation is simpler, but the signal-to-noise and distortion ratio deteriorates
Solution Approach 1:
The patent applies local quality by making different parts of the capacitor array have different properties. Specifically, capacitors connected to the positive input terminal have different characteristics than those connected to the negative input terminal. This localized differentiation allows each side of the differential pair to be optimized for its specific function, compensating for transistor impedance variations locally at each comparator input while maintaining overall circuit simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances impedance matching between the positive and negative input terminals of the comparator, thereby improving the overall performance of the SAR ADC by reducing errors and distortion.
Implementation Method 1
The switch-capacitor DAC includes multiple capacitors and is configured to sample the analog input signal in the sampling phase
Implementation Method 2
The comparator is coupled to the switch-capacitor DAC and configured to compare outputs of the switch-capacitor DAC to generate multiple comparison results
Data Source
AI summary
A successive approximation analog-to-digital converter (SAR ADC) and an operation method thereof are provided. The SAR ADC, which alternately operates in a sampling phase and a comparison and switching phase, includes a switch-capacitor digital-to-analog converter (DAC), a comparator, a successive approximation register and a control circuit. The switch-capacitor DAC including multiple capacitors. The control circuit is configured to (A) control a top plate of a first capacitor and a top plate of a second capacitor to be coupled to an analog input signal during the sampling phase; (B) control the first capacitor and the second capacitor to be active and inactive, respectively, in the comparison and switching phase according to a reference code after the sampling phase finishes; and (C) switch a terminal voltage of at least one of the capacitors during the comparison and switching phase according to the comparison results of the comparator.