SAR ADC Input Node Precharge for Kick-Back Noise Suppression
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Solution Overview
Problem
Successive approximation analog-to-digital converters face challenges in reducing kick-back noise during sampling, which affects conversion accuracy, often requiring large-capacity capacitors that restrict the input signal bandwidth and increase current consumption.
Innovation Solution
Incorporating an adjustment capacitor that supplies a voltage corresponding to the adjustment voltage to the input node before next sampling, suppressing voltage changes at the capacitors' ends and minimizing kick-back noise without the need for large-capacity capacitors or high slew rate buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large-capacity capacitors are used to reduce kick-back noise during sampling, then conversion accuracy is improved, but input signal bandwidth is restricted and current consumption increases
Solution Approach 1:
The adjustment capacitor performs preliminary action by supplying adjustment voltage to the input node before the sampling phase begins. This pre-charging of the input node with a predetermined voltage level prevents large voltage changes during sampling, thereby reducing kick-back noise without requiring large-capacity capacitors. The adjustment capacitor prepares the circuit state in advance to mitigate the harmful effects during the subsequent sampling operation.
2Measurement precision
If large-capacity capacitors are used to reduce kick-back noise during sampling, then conversion accuracy is improved, but current consumption increases
Solution Approach 1:
The adjustment capacitor performs preliminary action by supplying adjustment voltage to the input node before the sampling phase begins. This pre-charging of the input node with a predetermined voltage level prevents large voltage changes during sampling, thereby reducing kick-back noise without requiring large-capacity capacitors. The adjustment capacitor prepares the circuit state in advance to mitigate the harmful effects during the subsequent sampling operation.
3Measurement precision
If high slew rate buffer circuits are used to reduce kick-back noise, then conversion accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The adjustment capacitor performs preliminary action by supplying adjustment voltage to the input node before the sampling phase begins. This pre-charging of the input node with a predetermined voltage level prevents large voltage changes during sampling, thereby reducing kick-back noise without requiring large-capacity capacitors. The adjustment capacitor prepares the circuit state in advance to mitigate the harmful effects during the subsequent sampling operation.
Solution Approach 2:
The invention extracts and removes the need for complex high slew rate buffer circuits by using a simpler adjustment capacitor mechanism. By taking out the complex buffer circuit requirement and replacing it with the adjustment capacitor that performs preliminary voltage supply, the device complexity is reduced while maintaining the ability to suppress kick-back noise effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces kick-back noise during sampling, maintaining high conversion accuracy without restricting the input signal bandwidth and minimizing power consumption.
Implementation Method 1
an adjustment capacitor charged with an adjustment voltage, and supplies the analog signal to the plurality of capacitors through the input node to sample the analog signal... the adjustment capacitor supplies a voltage corresponding to the adjustment voltage to the input node before next sampling is performed after the successive approximation
Data Source
AI summary
Provided is a successive approximation analog-to-digital converter including a capacitive digital-to-analog converter that samples an analog signal corresponding to the analog input signal and that generates an analog output signal corresponding to a sampling result and a digital input, a comparator that compares the analog output signal and a comparison standard voltage, and a control circuit that generates the digital input corresponding to a comparison result obtained by the comparator, in which the capacitive digital-to-analog converter includes an input node that receives the analog signal, a plurality of capacitors, and an adjustment capacitor charged with an adjustment voltage, and supplies the analog signal to the plurality of capacitors through the input node to sample the analog signal, and the adjustment capacitor supplies a voltage corresponding to the adjustment voltage to the input node before next sampling is performed after the successive approximation.