Configurable SAR ADC Input Switching for Stable LSB Voltage
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Solution Overview
Problem
Conventional SARADC configurations face challenges in supporting single-ended inputs while maintaining the same LSB voltage and output code range as differential inputs, leading to reduced input range and increased power consumption.
Innovation Solution
A single-end input configurable SARADC is designed with a single-end P/N configure circuit that controls capacitive DAC switches and common-mode voltage switches, allowing the ADC to operate in differential, P single-ended, or N single-ended modes without additional circuitry or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-ended input configuration is used in differential SARADC, then the ADC can support single-ended input, but the input range is reduced by half and the LSB voltage becomes half of the differential mode
Solution Approach 1:
The patent implements dynamic configuration of the capacitive DAC through control logic that adjusts switch connections based on input mode selection. In single-ended mode, the DAC dynamically reconfigures which capacitors connect to reference voltage versus ground, enabling the same hardware to maintain full input range and LSB voltage for both differential and single-ended inputs without physical modification
Solution Approach 2:
The patent changes the electrical connection parameters of the capacitive DAC switches based on operating mode. By controlling the switch states to connect capacitors to different voltage rails (reference vs. ground) depending on whether differential or single-ended input is selected, the system maintains consistent performance characteristics across different input configurations
2Adaptability or versatility
If conventional single-ended input configuration is used in differential SARADC, then the ADC can support single-ended input, but the comparator common-mode voltage changes with respect to reference voltage and input during binary search
Solution Approach 1:
The control logic dynamically adjusts the common-mode voltage reference during the binary search process based on the detected input mode. This dynamic adjustment ensures that the comparator always operates with a stable common-mode voltage level regardless of whether differential or single-ended input is being processed
Solution Approach 2:
The system uses feedback from the mode detection logic to continuously adjust the common-mode voltage setting during conversion. The control logic monitors the operating mode and provides real-time adjustment to maintain stable comparator operation throughout the binary search process
3Measurement precision
If an amplifier is added to convert single-ended input to differential inputs, then the input range and LSB voltage are maintained, but power consumption increases and additional circuitry is required
Solution Approach 1:
The patent makes the capacitive DAC universal by implementing mode-dependent configuration logic that enables the same hardware circuit to perform both differential and single-ended input conversions. The control logic selectively activates appropriate switch connections based on input mode, eliminating the need for separate amplifier circuitry while maintaining full functionality for both input types
Solution Approach 2:
The differential SARADC structure serves itself by using its existing capacitive DAC and control logic to natively support both differential and single-ended inputs. The system's own control mechanism configures the appropriate connections without requiring external conversion circuitry, thereby avoiding additional power consumption and circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution maintains consistent LSB voltage and output code range across different input modes, reduces power consumption, and minimizes common-mode voltage variation during binary search, addressing the limitations of conventional configurations.
Implementation Method 1
N-bit DAC is initially set to midscale (100 . . . 00), resulting in the DAC output, VDAC, being equal to VR/2, where VR is the reference voltage. As the first step of the binary-search process begins, the MSB capacitor C11 is connected to reference voltage VR and the rest of capacitors C10 ̃C0 are grounded. This drives the voltage of comparator inputs by an amount of 0.5VR owing to the principle of charge redistribution.
Data Source
AI summary
A single-end input configurable Successive Approximation Register Analog-to-Digital Converter (SARADC) allows for the input configuration as single-ended or differential inputs without adding extra circuitry. In both configurations, the ADC maintains the same LSB voltage and output code range. Furthermore, when configured as a single-ended input, power consumption is further reduced.