SAR ADC Chopping Using Inverse-Code Charge Redistribution
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in reducing comparator flicker noise and input settling effects, which degrade signal quality in low-frequency wireless communication applications, such as GSM or narrowband carriers in 4G/5G networks, without increasing area and power consumption.
Innovation Solution
The implementation of a SAR ADC with a charge redistribution mechanism, where inverse digital codes are applied to capacitive arrays via reference buffers, allowing the capacitors to quickly discharge and reset, enabling chopping of the input signal without affecting signal linearity or amplitude, and reducing the impact of comparator flicker noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SAR ADC architecture is used, then area and power efficiency are maintained, but comparator flicker noise and input settling effects degrade signal quality
Solution Approach 1:
The patent applies chopping technique that periodically switches the comparator inputs between the differential signal and ground reference. This periodic switching moves the comparator flicker noise to higher frequencies where it can be filtered out, while maintaining the original signal integrity. The switch alternates between connecting the signal to the comparator and connecting a reference voltage, creating a modulated signal that separates noise from the desired frequency range.
Solution Approach 2:
The patent introduces an intermediary charging mechanism using capacitive arrays and reference buffers that apply inverse digital codes to redistribute charges on the capacitive arrays. This intermediary charge redistribution process prepares the capacitors before each conversion cycle, ensuring they start in a known state and reducing input settling effects that would otherwise degrade signal quality.
2Reliability
If charge redistribution mechanism is added, then comparator flicker noise is reduced, but device complexity increases
Solution Approach 1:
The patent integrates the charge redistribution function into the existing SAR ADC capacitive arrays, making them serve dual purposes: both for the standard binary search conversion process and for the pre-charging/reset function. The same capacitive elements used for signal conversion also store and redistribute charge during the chopping cycles, eliminating the need for separate dedicated reset capacitors or additional complex circuitry.
Solution Approach 2:
The patent combines the reference buffer function with the existing DAC capacitive array structure. The reference buffer that applies inverse digital codes is integrated into the same capacitive network used for signal conversion, merging multiple functions into a unified circuit architecture. This reduces the total component count and simplifies the overall design while achieving noise reduction.
3Reliability
If chopping is applied to reduce flicker noise, then signal quality improves, but input settling effects may worsen
Solution Approach 1:
The patent applies preliminary charging action before each conversion cycle by redistributing charges on the capacitive arrays using inverse digital codes. This pre-charging ensures that the capacitors start each conversion cycle in a known, standardized state, eliminating the need for long settling times. The charge redistribution happens in advance, so when the actual conversion begins, the inputs are already settled and stable.
Solution Approach 2:
The patent uses feedback through the reference buffer that applies inverse digital codes based on the previous conversion result. This feedback mechanism ensures that any residual charge or voltage offset from the previous cycle is corrected before the next conversion, maintaining consistent starting conditions and reducing settling time requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces comparator flicker noise and input settling effects, maintaining signal quality while maintaining the area and power efficiency of the SAR ADC architecture, allowing for efficient chopping of input signals in wireless communication systems.
Implementation Method 1
the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer
Data Source
AI summary
Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.