SAR ADC Switch Control for Comparator Kickback Noise Reduction
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Solution Overview
Problem
Conventional SAR ADCs suffer from kickback noise due to impedance mismatch between the input terminals of the comparator, leading to incorrect comparison results and poor performance.
Innovation Solution
A control circuit for SAR ADCs is introduced, featuring a buffer circuit that controls switches to ensure better impedance matching between the target capacitor's terminals and reference voltages, using a third switch and buffer circuit to manage the switching of sub-control signals, allowing the second switch to turn on before the first switch, thereby reducing equivalent impedance mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switch control is used in SAR ADC, then device complexity is reduced, but impedance mismatch between comparator input terminals causes kickback noise and incorrect comparison results
Solution Approach 1:
A buffer circuit is introduced as an intermediary between the control signal and the switch control signals. The buffer circuit generates complementary switch control signals (G1-Gn and #G1-#Gn) that ensure proper timing and impedance matching, eliminating kickback noise without significantly increasing overall system complexity
Solution Approach 2:
The buffer circuit preliminarily processes the control signal to generate properly timed switch control signals before the switches are activated. This preliminary action ensures that switches are controlled in the correct sequence (first switch turns on before second switch), preventing impedance mismatch and kickback noise before they can occur
2Object-affected harmful factors
If switch timing is not optimized, then device complexity is minimized, but kickback noise occurs due to impedance mismatch
Solution Approach 1:
The buffer circuit acts as a mediator that coordinates the timing of complementary switch control signals, ensuring that switches are activated in the correct sequence to maintain impedance matching and eliminate kickback noise
Solution Approach 2:
The buffer circuit generates periodic complementary control signals that systematically control the switching sequence. This periodic action ensures consistent timing relationships between switch activations, maintaining proper impedance matching throughout operation
3Productivity
If faster stabilization is achieved through optimized switching, then productivity increases, but device complexity increases due to additional control circuits
Solution Approach 1:
The buffer circuit preliminarily generates properly timed control signals that enable faster switching stabilization. By pre-processing the control signal to establish correct timing relationships, the system achieves faster ADC operation without requiring complex additional control mechanisms
Data Source
AI summary
A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.