SAR ADC Latch Circuit With One-Gate-Delay DAC Wiring
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Solution Overview
Problem
Existing successive-approximation register analog-to-digital converters (SAR ADCs) face challenges in speeding up the successive approximation process, which affects their overall performance and efficiency.
Innovation Solution
The proposed SAR ADC design incorporates a digital-to-analog converter (DAC), a comparator, and a SAR logic circuit with a one-gate-delay circuit in each latch, using complex gates such as OR-AND-INVERTER (OAI) or AND-OR-INVERTER (AOI) gates to wire the comparator to the DAC, thereby reducing delay and enhancing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wiring is used between comparator and DAC in SAR ADC, then device complexity is reduced, but conversion speed decreases due to increased delay
Solution Approach 1:
The patent divides the SAR logic circuit into multiple latches, with each latch containing a one-gate-delay circuit that independently wires the comparator to a specific bit-control terminal of the DAC. This segmentation allows each latch to operate with minimized delay while maintaining overall system functionality.
Solution Approach 2:
The one-gate-delay circuit acts as an intermediary component between the comparator and the DAC bit-control terminals. This intermediary structure reduces the propagation delay by providing a direct, optimized wiring path through the complex gate, while the latch structure manages the control signals appropriately.
2Productivity
If one-gate-delay circuit is implemented in each latch, then conversion speed increases, but device complexity increases
Solution Approach 1:
The patent merges the delay reduction function with the existing latch structure by integrating the one-gate-delay circuit directly into each latch. This combination allows the circuit to perform both latching and delay minimization functions simultaneously, improving productivity without adding separate delay compensation stages.
Solution Approach 2:
The one-gate-delay circuit within each latch serves multiple functions: it acts as part of the latch structure, provides delay reduction, and controls the bit-line signals to the DAC. This multi-functionality improves conversion efficiency while limiting the increase in overall device complexity.
3Loss of time
If complex gates (OAI/AOI) are used to wire comparator to DAC, then delay is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the logical parameters by using complex gates (OAI or AOI) instead of simple gates, which alters the signal propagation characteristics. This parameter change reduces the delay by optimizing the logic path, while the standard CMOS fabrication processes maintain reasonable manufacturing precision requirements.
Data Source
AI summary
A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.