SAR ADC Latch Feedback for DAC Settling Margin
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Solution Overview
Problem
High-speed SAR ADC architectures often provide insufficient time for the digital-to-analog converter (DAC) to settle, leading to conversion errors due to limited time margin for settling.
Innovation Solution
A successive-approximation register (SAR) ADC circuit utilizing a series of latch circuits to implement a successive-approximation algorithm, where each latch circuit can trigger the next one before the comparator output becomes valid, thereby reducing the time delay and allowing more time for the DAC to settle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed SAR ADC architecture is used to increase sampling rate, then productivity is improved, but the time margin for DAC settling is insufficient leading to conversion errors
Solution Approach 1:
The patent applies preliminary action by triggering the next latch circuit before the current comparator output becomes valid. The latch circuit is enabled in advance to capture the comparator output once it settles, rather than waiting for validation. This advance triggering provides additional time margin for the DAC to settle during high-speed operation, preventing conversion errors while maintaining high sampling rates.
2Reliability
If conventional latch triggering is used where next latch is triggered after current comparator output is valid, then reliability is maintained, but time margin for DAC settling is insufficient
Solution Approach 1:
The patent enables the next latch circuit in advance before the current comparator output becomes valid. This preliminary enabling allows the latch to be ready to capture the comparator output immediately when it settles, rather than waiting for validation. This approach recovers time margin for DAC settling without compromising conversion accuracy.
3Loss of time
If latch circuit is enabled before comparator output is valid, then time margin for DAC settling is increased, but risk of capturing invalid data increases
Solution Approach 1:
The patent uses feedback through the valid signal that monitors whether the comparator output is valid. The latch circuit is enabled in advance but only captures data when the valid signal indicates the comparator output is ready. This feedback mechanism ensures that even though the latch is enabled early, it will not capture invalid data, maintaining reliability while increasing time margin for DAC settling.
Data Source
AI summary
A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.