SAR ADC Latch Sequencing for DAC Settling Margin
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Solution Overview
Problem
High-speed SAR ADC architectures often provide insufficient time margin for the digital-to-analog converter (DAC) settling time, leading to conversion errors due to the limited time allowed for DAC settling.
Innovation Solution
The proposed SAR ADC circuit employs a series of latch circuits connected to a comparator circuit, where each latch can trigger the next latch before the comparator output becomes valid, thereby reducing the time delay and allowing sufficient time for DAC settling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed SAR ADC architecture is used to increase sampling rate, then productivity is improved, but the time margin for DAC settling becomes insufficient leading to conversion errors
Solution Approach 1:
The patent applies preliminary action by enabling the first latch circuit before the comparator output becomes valid, and using delay stages to advance the triggering of subsequent latch circuits. This allows the latching process to begin in advance, giving the DAC sufficient settling time even at high sampling rates, thereby maintaining conversion accuracy while preserving high productivity
2Device complexity
If conventional SAR ADC control scheme is used, then device complexity is kept simple, but the time margin for DAC settling is insufficient
Solution Approach 1:
The patent segments the latching process into multiple independent latch circuits (first latch circuit, second latch circuit, etc.) with delay stages between them. This segmentation allows each latch to be triggered at optimally different times, providing sufficient settling time for the DAC while maintaining overall system simplicity through modular design
Solution Approach 2:
Delay stages are used to advance the triggering of subsequent latch circuits before the comparator output becomes valid. This preliminary action ensures that the latching sequence is already in progress when the DAC finishes settling, eliminating timing constraints without adding complex control logic
Data Source
AI summary
A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.