SAR ADC Overlapping Voltage Ranges for Lower-Latency Conversion
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Solution Overview
Problem
Conventional SAR ADC architectures use reference voltages equal to the maximum input voltage, which affects power consumption and latency due to the number of clock cycles required for conversion, and do not efficiently handle varying input voltages.
Innovation Solution
A SAR ADC with a reference voltage set to half the difference between the maximum and minimum input voltage, using a comparator and DAC with capacitors and switches to generate digital representations of analog inputs by adjusting voltage levels based on comparator outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the reference voltage is set equal to the maximum input voltage, then the ADC can handle the full input voltage range, but power consumption increases and conversion latency increases
Solution Approach 1:
The patent changes the reference voltage parameter from the conventional maximum input voltage to a value approximately equal to half the voltage difference between maximum and minimum input voltages. This parameter change reduces the voltage swing required in the CDAC, thereby reducing power consumption while maintaining the ability to handle varying input voltages through overlapping reference voltage ranges.
2Adaptability or versatility
If the reference voltage is set equal to the maximum input voltage, then the ADC can handle the full input voltage range, but the number of clock cycles required for conversion increases
Solution Approach 1:
The patent changes the reference voltage parameter to reduce the voltage swing required during conversion. By setting the reference voltage to approximately half the voltage difference between maximum and minimum input voltages, the SAR logic can complete the successive approximation process in fewer clock cycles, thereby reducing conversion latency.
3Use of energy by moving object
If the reference voltage is reduced to half the voltage difference between maximum and minimum input voltages, then power consumption decreases, but the ability to handle varying input voltages may be compromised
Solution Approach 1:
The patent segments the reference voltage into multiple ranges, including a first reference voltage range and a second reference voltage range that overlap. This segmentation allows the ADC to handle varying input voltages across different ranges while using lower reference voltages to reduce power consumption. The overlapping ranges ensure continuous coverage of the full input voltage range.
Solution Approach 2:
The patent implements dynamic switching between different reference voltage ranges based on the input voltage level. The SAR logic selectively uses the first or second reference voltage range depending on the analog input voltage, allowing the system to adapt to varying input conditions while maintaining low power consumption through optimized reference voltage selection.
Data Source
AI summary
An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.