SAR ADC Sampling Circuit for Summing Node Leakage Control
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Solution Overview
Problem
Conventional switched capacitor circuits and SAR ADCs face issues with charge leakage through substrate diodes due to analog summing node voltages exceeding safe operating ranges, requiring costly boosting and modification of the SAR algorithm, which affects signal integrity and increases complexity.
Innovation Solution
A switched-capacitor circuit that maintains a predetermined common mode voltage on summing conductors, canceling common mode input voltage components and preventing charge leakage by coupling capacitors to reference voltages, thereby keeping summing node voltages within a safe range without the need for boosting or modifying the SAR algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switched capacitor circuits are used without voltage control, then the circuit is simpler and less costly, but charge leakage occurs through substrate diodes due to summing node voltages exceeding safe operating ranges
Solution Approach 1:
The patent applies preliminary action by establishing a fixed common mode voltage component on the summing conductor before the SAR conversion process begins. This is achieved by connecting capacitors to reference voltages during the sampling phase, which pre-establishes the voltage conditions needed to prevent charge leakage through substrate diodes during subsequent conversion operations.
Solution Approach 2:
The patent changes the voltage parameter of the summing node by introducing a fixed common mode voltage component. This is accomplished through capacitor connections to reference voltages (VREF and VSS), which establish a predetermined voltage level that keeps the summing node within the safe operating range throughout the conversion process.
2Reliability
If boosting circuitry is added to maintain summing node voltages within safe range, then charge leakage is prevented, but the circuit becomes more complex and costly
Solution Approach 1:
The patent applies self-service by using the existing SAR algorithm and standard capacitor switching mechanisms to automatically maintain the summing node voltage within the safe operating range. The fixed common mode voltage component works in conjunction with the normal SAR conversion process, eliminating the need for separate boosting circuitry or voltage monitoring systems.
Solution Approach 2:
The patent makes the capacitor network serve multiple functions: it performs the standard SAR conversion function while simultaneously establishing a fixed common mode voltage to prevent charge leakage. This multi-functionality eliminates the need for dedicated boosting circuitry, as the same capacitors and switches used for conversion also maintain safe operating voltages.
3Reliability
If the SAR algorithm is modified to accommodate voltage constraints, then charge leakage is prevented, but the conversion process becomes more complex and time-consuming
Solution Approach 1:
The patent applies preliminary action by establishing the fixed common mode voltage component during the sampling phase, before the SAR conversion process begins. This pre-establishment of voltage conditions ensures that the standard SAR algorithm can proceed without modifications or interruptions, maintaining optimal conversion speed.
Solution Approach 2:
The patent uses periodic action by maintaining the fixed common mode voltage throughout the entire conversion process through continuous capacitor connections to reference voltages. This periodic maintenance of voltage conditions allows the SAR algorithm to operate at full speed without requiring intermediate voltage adjustments or algorithmic interruptions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents charge leakage through substrate diodes, maintains signal integrity, reduces complexity and cost, and avoids the need for additional circuitry to monitor and control common mode voltages, enhancing the reliability and efficiency of the SAR ADC.
Implementation Method 1
A first terminal (top plate) of a first capacitor (C1) is connected to receive a first input signal (VIN+) during sampling; A second terminal (bottom plate) of the first capacitor (C1) is switched to the first reference voltage (VSS) during sampling, to a second reference voltage (VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the first conductor (13), establish a predetermined common mode voltage component on the first conductor (13)
Implementation Method 2
analog summing node voltages swinging outside of an acceptable range in a switched capacitor circuit, an SAR ADC, and still more particularly to SAR ADCs that are simpler and less expensive than those available in the prior art
Data Source
AI summary
A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.