Segmented SAR ADC Coding for Capacitor Mismatch Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Precision analog-to-digital converters face challenges in achieving high linearity due to capacitor mismatch errors, which can result in nonlinearity and deviation from desired statistical properties, especially in applications requiring accurate conversion of analog signals.
Innovation Solution
The proposed solution involves an analog-to-digital converter (ADC) that derives a first code approximating the combination of an analog input value and a dither value, and then uses a second code to represent the residue, combining these codes digitally to improve linearity by applying them to a capacitor array, thereby reducing the impact of capacitor mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor ratios are used in a CDAC for SAR ADC, then the ADC can achieve high conversion speed and resolution, but capacitor mismatch errors cause nonlinearity and degrade conversion precision
Solution Approach 1:
The capacitor array is divided into multiple segments, each segment being converted separately. The conversion result is then reconstructed by combining the segment results. This segmentation allows each segment to use simpler capacitor ratios (reducing mismatch sensitivity) while maintaining overall high resolution through the combination of multiple segments.
Solution Approach 2:
An intermediate digital code is generated for each capacitor segment during the conversion process. These intermediate codes serve as mediators that capture the analog-to-digital transition information. The final high-precision digital output is reconstructed by combining these intermediate codes, avoiding the need for perfectly matched high-ratio capacitors.
2Measurement precision
If high-ratio capacitor values are used in CDAC, then higher resolution can be achieved, but capacitor mismatch and fabrication variations increase causing nonlinearity errors
Solution Approach 1:
Instead of using a single capacitor array with high-ratio values, the system uses multiple capacitor segments with lower, more achievable ratio values. Each segment's conversion result is combined to achieve the overall high resolution, bypassing the need for precise high-ratio capacitor fabrication.
Solution Approach 2:
Multiple capacitor segments are used as copies, each performing a portion of the conversion function. Rather than relying on a single high-precision capacitor array, the system creates multiple lower-precision copies that together achieve the desired overall precision through their combined output.
3Device complexity
If conventional SAR ADC conversion is used, then simple circuit structure is maintained, but nonlinearity errors from capacitor mismatch limit conversion accuracy
Solution Approach 1:
The conversion process is segmented into multiple stages, with each stage handling a portion of the conversion. This segmentation adds computational steps but maintains relatively simple circuit structures within each segment, achieving high accuracy through the combination of multiple simple conversion results.
Solution Approach 2:
The conversion process continues with multiple segments being converted and their results combined, rather than completing the conversion in a single step. This continuous process of conversion and combination maintains simple circuitry while improving accuracy through multiple measurement and combination cycles.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.