Pipelined Subranging SAR ADC for Low-Power High-Resolution Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face challenges in balancing resolution and bandwidth with power consumption, as increasing resolution and bandwidth often requires undesirable increases in power consumption.
Innovation Solution
The proposed solution involves a pipelined subranging SAR ADC system with a coarse stage that reduces accuracy requirements, allowing the fine stage to be used only for a portion of the conversion period, thereby reducing overall power consumption while maintaining high energy efficiency and linearity. This system includes a first ADC stage that converts the most significant bits and outputs an analog residue signal, which is then amplified and converted by a second ADC stage, optimizing the conversion rate and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution and bandwidth of the ADC are increased, then the conversion performance is improved, but the power consumption increases undesirably
Solution Approach 1:
The ADC is divided into two separate stages: a coarse stage that handles the most significant bits and a fine stage that handles the least significant bits. This segmentation allows each stage to be optimized independently, with the coarse stage operating at lower precision and the fine stage operating at higher precision only when needed, thereby reducing overall power consumption while maintaining high resolution performance.
Solution Approach 2:
The fine stage is dynamically activated only during specific portions of the conversion period when high-precision conversion is required, rather than operating continuously. This dynamic operation allows the system to maintain high resolution capability when needed while minimizing power consumption during periods when full precision is not required.
2Productivity
If the sampling rate is increased to improve bandwidth, then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
The fine stage operates periodically rather than continuously, being activated only during specific phases of the conversion process when high-precision conversion is required. This periodic operation enables the system to achieve high conversion rates when needed while minimizing power consumption during other phases, effectively decoupling conversion rate from continuous power consumption.
3Manufacturing precision
If the accuracy requirements of the ADC are increased, then the linearity is improved, but the device complexity increases
Solution Approach 1:
The linearity requirement is segmented between two stages: the coarse stage handles the bulk of the conversion with relaxed linearity requirements, while the fine stage provides the high-precision linearity correction for the least significant bits. This segmentation allows the system to achieve high overall linearity without requiring both stages to meet stringent linearity specifications, thereby reducing device complexity.
Data Source
AI summary
An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.