Split-Capacitor SAR ADC Calibration for Accurate LSB Weight

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Solution Overview

Problem

Conventional split capacitor SAR ADCs are difficult to calibrate due to the LSB weight not being a function of comparator decisions, making it challenging to estimate the LSB weight, which is crucial for pipeline ADC performance.

Innovation Solution

A calibration scheme for SAR ADCs that involves n+1 calibration measurements to determine the weight of each bit, including adjusting switch connections to estimate the LSB weight by detecting threshold crossings in comparison signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional split capacitor SAR ADC architecture is used, then area efficiency and power consumption are improved, but calibration difficulty increases due to LSB weight not being a function of comparator decisions

Engineering Contradiction:
Improvepower consumptionVSAvoidcalibration complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing calibration measurements before normal ADC operation. The calibration phase systematically determines LSB weight and capacitor mismatch parameters in advance, allowing the ADC to operate with pre-characterized parameters during conversion, thus resolving the calibration difficulty while maintaining area efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary calibration signal that is injected into the ADC input during calibration mode. This calibration signal serves as a mediator to probe the internal capacitor weights and comparator thresholds, enabling indirect measurement of LSB weight without requiring direct access to comparator decision functions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If conventional split capacitor SAR ADC architecture is used, then area efficiency is improved, but measurement precision deteriorates due to difficulty in estimating LSB weight

Engineering Contradiction:
Improvearea efficiencyVSAvoidLSB weight estimation precision
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent implements feedback by using the comparator output decisions during calibration to refine the estimated LSB weight. The calibration process feeds back the comparator responses to adjust and verify the measured capacitor weights, ensuring precise LSB weight estimation while maintaining the area-efficient split capacitor architecture

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies partial action by performing multiple calibration measurements (n+1 measurements for n-bit ADC) to progressively refine the LSB weight estimate. Rather than requiring a single perfect measurement, the system accumulates information from multiple partial measurements to achieve high precision LSB weight estimation

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3843275B1N-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
Publication Date: 2025.08.27 INTEL CORP
  • EP3843275B1 patent drawingFigure 1
  • EP3843275B1 patent drawingFigure 2
  • EP3843275B1 patent drawingFigure 3

AI summary

A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.