SAR ADC Digital Offset Correction for Memory Cell Comparators
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Solution Overview
Problem
Successive approximation type analog-to-digital converters face challenges in reducing offset errors in memory cell rewriting type comparators, which increase layout area and current consumption, and existing correction methods complicate the circuit layout.
Innovation Solution
Incorporating a correction circuit with a non-volatile memory to store and apply offset correction values to the conversion data generated by a memory cell rewriting type comparator, allowing for digital addition or subtraction of fixed offset correction values to eliminate output errors without increasing layout area or current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gate width of the MOS transistor in the first stage operational amplifier is increased to reduce offset error, then the offset error decreases, but the current consumption increases and the layout area increases
Solution Approach 1:
The patent applies preliminary action by measuring and storing the offset error of each comparator in a non-volatile memory during manufacturing or initialization. This pre-measured offset value is then retrieved and applied for correction during normal operation, eliminating the need to use larger transistors to reduce offset error, thereby maintaining low current consumption while achieving high measurement precision.
Solution Approach 2:
The patent changes the parameter approach from physical transistor dimensions to digital correction values. Instead of physically increasing gate width to reduce offset, the system measures the actual offset and applies a digital correction parameter (stored offset value) to compensate, allowing small transistors to achieve the same effective precision as much larger ones would provide physically.
2Measurement precision
If the gate width of the MOS transistor in the first stage operational amplifier is increased to reduce offset error, then the offset error decreases, but the layout area increases
Solution Approach 1:
The patent applies preliminary action by measuring and storing the offset error of each comparator in a non-volatile memory during manufacturing or initialization. This pre-measured offset value is then retrieved and applied for correction during normal operation, eliminating the need to use larger transistors to reduce offset error, thereby maintaining small layout area while achieving high measurement precision.
Solution Approach 2:
The patent changes the parameter approach from physical transistor dimensions to digital correction values. Instead of physically increasing gate width to reduce offset, the system measures the actual offset and applies a digital correction parameter (stored offset value) to compensate, allowing small transistors to achieve the same effective precision as much larger ones would provide physically.
3Measurement precision
If offset correction capacitive elements with switches are added to the L and R nodes, then the offset error is corrected, but the layout area increases significantly
Solution Approach 1:
The patent replaces the mechanical/analog offset correction system (capacitive elements with switches connected to L and R nodes) with a digital correction system. Instead of using physical capacitors and switches that occupy significant layout area, the system uses digitally stored offset values that are applied through simple addition/subtraction logic, dramatically reducing the layout area required for offset correction while maintaining correction effectiveness.
4Measurement precision
If a correction circuit is added to the comparator to correct offset error, then the offset error is reduced, but the layout area and circuit complexity increase
Solution Approach 1:
The patent replaces complex analog correction circuits with a simple digital correction mechanism. Instead of adding analog components like capacitors, switches, and additional operational amplifiers, the system uses a non-volatile memory to store offset values and a simple digital adder/subtractor to apply corrections, significantly reducing circuit complexity while achieving the same offset error reduction.
Data Source
AI summary
One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.