Asynchronous SAR ADC Timing Control for Meta-Stability Bias
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Solution Overview
Problem
Asynchronous SAR ADCs suffer from meta-stability issues, leading to significant digitization errors and impaired bit-error-ratio performance due to non-Gaussian error statistics, which current techniques have not adequately addressed.
Innovation Solution
The implementation of a detector that accelerates asynchronous bit cycles in SAR ADCs by reducing adjustable delays or time limits when meta-stability error biases exceed a threshold, using a counter to measure LSB assertions and a filter to adapt bit cycles, thereby limiting meta-stability errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous bit cycles are used in SAR ADC for fast conversion, then conversion speed is improved, but meta-stability errors increase
Solution Approach 1:
The patent implements a feedback mechanism where the detector monitors LSB assertions from the SAR ADC output and uses this information to dynamically adjust the bit cycle duration. When meta-stability errors are detected (indicated by abnormal LSB assertion patterns), the system automatically lengthens the bit cycle time to allow comparators more time to resolve uncertain comparisons, thereby reducing error rates while maintaining high-speed operation during normal conditions
Solution Approach 2:
The patent makes the bit cycle duration dynamic rather than fixed. The detector continuously monitors the output statistics and adjusts the timing parameters in real-time based on detected error patterns. This dynamic adaptation allows the system to optimize between speed and reliability by extending bit cycles only when meta-stability issues are detected, rather than operating at conservative fixed timing throughout
2Reliability
If comparator decision time is extended to reduce meta-stability errors, then reliability is improved, but conversion speed decreases
Solution Approach 1:
The patent applies partial action by extending the bit cycle duration only when necessary, rather than always using excessive timing margins. The detector monitors LSB assertion patterns to identify when meta-stability errors are occurring, and only then does it lengthen the bit cycle time. During normal operation with sufficient timing margin, the system maintains faster conversion speeds, thus avoiding the performance penalty of consistently conservative timing
3Difficulty of detecting and measuring
If detector monitors LSB assertions to detect meta-stability errors, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by using the SAR ADC's own output (LSB assertions) as the monitoring signal. The detector leverages the existing digital output from the ADC rather than requiring separate monitoring circuits or additional sensors. This approach detects meta-stability errors by analyzing patterns in the normal operational output, eliminating the need for complex dedicated error detection hardware while maintaining effective monitoring capability
Data Source
AI summary
Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.