Asynchronous SAR ADC Metastability Compensation in DSM Loops
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Asynchronous successive-approximation-register (SAR) ADCs in delta sigma modulators face metastability issues, which can halt the conversion process and degrade Signal to Noise Ratio (SNR), and existing solutions add complexity, power consumption, and delay.
Innovation Solution
A metastability detector and compensator circuitry are implemented, using a reference clock offset from the ADC clock to detect metastability and apply compensation schemes, such as using last valid data or averaging prior samples, to prevent ADC instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If legacy approaches add extra comparators to address metastability, then metastability detection capability is improved, but device complexity and area increase
Solution Approach 1:
The patent introduces a metastability detector as an intermediary component that monitors the SAR ADC operation without requiring additional comparators. The detector uses the existing comparator output and clock signals to identify metastability conditions, acting as a mediator between the SAR ADC and the control logic to prevent metastability propagation.
Solution Approach 2:
The patent implements a feedback mechanism where the metastability detector monitors the conversion process and provides feedback signals to control logic. When metastability is detected, the feedback triggers compensation actions such as extending the conversion time or re-initiating the conversion, creating a closed-loop system that automatically corrects metastability issues without adding comparators.
2Reliability
If legacy approaches add comparators to detect metastability, then metastability detection is improved, but power consumption increases
Solution Approach 1:
The metastability detector is designed to self-service by utilizing existing circuit resources rather than requiring additional power-hungry components. It leverages the existing comparator output signals and clock infrastructure to perform detection, and the compensation mechanism uses digital logic that consumes minimal power compared to analog comparator circuits.
Solution Approach 2:
The detector acts as a low-power intermediary that processes digital signals from the existing comparator rather than requiring additional high-power analog comparators. The use of digital logic and flip-flops in the detection circuitry significantly reduces power consumption compared to legacy analog approaches.
3Reliability
If legacy approaches use subsequent clock cycles to detect metastability, then metastability detection is improved, but conversion delay increases
Solution Approach 1:
The patent implements preliminary action by having the metastability detector continuously monitor conversion status during the normal conversion process. The detector is prepared in advance with the appropriate timing logic to immediately identify metastability conditions as they occur, rather than waiting for subsequent clock cycles after conversion completes. This allows for real-time detection and immediate compensation.
Solution Approach 2:
The feedback mechanism provides real-time metastability detection during the conversion process itself. When metastability is detected, the feedback signal immediately triggers compensation actions such as extending the conversion time or re-initiating the conversion, preventing delay propagation to the output rather than detecting the delay after it has occurred.
4Use of energy by moving object
If asynchronous SAR ADC is used to eliminate high frequency clocks, then power efficiency is improved, but metastability issues worsen
Solution Approach 1:
The patent implements a feedback-based metastability compensation system that monitors the asynchronous SAR ADC operation and automatically corrects metastability issues. The metastability detector provides feedback to control logic that can extend conversion time or re-initiate conversions when metastability is detected, maintaining conversion stability without requiring high-frequency clocks or additional comparators.
Solution Approach 2:
The metastability detector and compensation logic serve as intermediaries between the asynchronous SAR ADC and the digital output interface. This intermediary layer handles the metastability management, allowing the asynchronous ADC to operate efficiently while ensuring stable, metastability-free output data.
Data Source
AI summary
Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.