Asynchronous SAR ADC Word Completion for Metastability Control

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Solution Overview

Problem

Conventional analog-to-digital conversion methods are costly, cumbersome, inefficient, and prone to errors or distortion due to complex processes, high power consumption, and metastability issues in asynchronous successive approximation register (SAR) ADCs.

Innovation Solution

A photonically-enabled integrated circuit with an asynchronous successive approximation register analog-to-digital converter (ADC) employing a word completion algorithm, utilizing a metastability detector and tunable timer to manage metastability conditions, and a switched capacitor DAC for efficient bit-by-bit conversion, ensuring accurate digital signal processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional analog-to-digital conversion methods are used, then conversion functionality is provided, but the systems are costly, cumbersome, and inefficient with high power consumption

Engineering Contradiction:

Improveconversion efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces conventional synchronous ADC architectures with an asynchronous SAR ADC architecture that eliminates the need for high-speed clocking mechanisms and complex timing control circuits. The asynchronous operation uses event-driven sampling and conversion, substituting mechanical clock-based operation with signal-level handshaking, thereby reducing power consumption while maintaining conversion functionality

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The conversion process is segmented into independent bit-by-bit approximation steps, where each bit is converted separately through sequential comparison operations. This segmentation allows the system to perform conversions in smaller, more energy-efficient steps rather than requiring high-power simultaneous multi-bit processing, improving overall conversion efficiency

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If asynchronous SAR ADC is used to reduce power consumption, then energy efficiency is improved, but metastability conditions cause errors and distortion

Engineering Contradiction:

Improvepower consumptionVSAvoidconversion accuracy

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the output of each comparison stage is fed back to control subsequent conversion steps. This feedback ensures that metastability conditions are detected and handled appropriately, with the system adjusting its operation based on the stability of previous conversion results, thereby maintaining accuracy while operating asynchronously

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The design incorporates preliminary stabilization measures and validation checks before final conversion completion. By anticipating potential metastability issues and implementing protective logic in advance, the system can detect and correct errors before they propagate, ensuring reliable conversion results even in asynchronous operation

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Measurement precision

If complex conversion processes are used to improve accuracy, then measurement precision is improved, but the processes become cumbersome and time consuming

Engineering Contradiction:

Improveconversion accuracyVSAvoidconversion time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs conversion to a sufficient precision level rather than maximum possible precision. The successive approximation process stops when the required accuracy is achieved, performing only the necessary number of comparison steps. This partial action approach avoids unnecessary time consumption while maintaining adequate measurement precision for the application

Inventive Principle:

Principle #16Partial or excessive action

4Productivity

If high conversion rates are maintained, then productivity is improved, but power consumption increases and errors occur

Engineering Contradiction:

Improveconversion rateVSAvoidenergy efficiency

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The asynchronous SAR ADC operates with periodic conversion cycles triggered by input signal changes rather than continuous high-speed clocking. The conversion process activates only when needed, with idle periods between conversions where power consumption is minimized. This periodic operation maintains high effective conversion rates while significantly reducing average power consumption compared to continuous operation

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS11811419B2Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm

Publication Date: 2023.11.07 CISCO TECHNOLOGY INC

AI summary

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.