SAR ADC Comparator Circuit With Metastability Assist Latch
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Solution Overview
Problem
The SAR type AD converter circuit using a dynamic comparator experiences metastable states, leading to prolonged completion times for comparison determinations, which can result in incomplete AD conversion operations and incorrect results.
Innovation Solution
A differential comparison circuit with a determination assist circuit that varies output signals when a metastable state occurs, using logical sum operation circuits and buffers to generate delayed clock signals, ensuring timely completion of comparison determinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dynamic comparator is used in a SAR type AD converter circuit, then the comparison operation can be performed in synchronization with a clock signal, but metastable states occur leading to prolonged completion times for comparison determinations
Solution Approach 1:
A determination assist circuit is introduced as an intermediary component between the dynamic comparator and the latch circuit. This assist circuit includes OR circuits that receive comparison determination signals and delayed clock signals, and generate determination assist signals. The intermediary circuit ensures that comparison determinations are completed within the required time frame by forcing a determination result when the comparator remains in a metastable state, thus preventing incomplete AD conversion operations while maintaining synchronous operation with the clock signal.
2Ease of operation
If the comparison determination operation is performed using an internally generated clock signal, then the operation can be synchronized, but the metastable state causes long delays in obtaining comparison results
Solution Approach 1:
The determination assist circuit performs preliminary action by generating determination assist signals based on both the comparison determination signals and delayed clock signals before the final latching operation. The OR circuits in the assist circuit proactively prepare determination results that will be latched by the latch circuit, ensuring that the comparison result is ready within the required time frame. This preliminary action prevents time loss by having the determination result prepared in advance, even when the dynamic comparator is still in a metastable state.
3Adaptability or versatility
If the dynamic comparator operates asynchronously with internal clock generation, then the circuit can function independently, but the AD conversion operation may not complete within the specified comparison period
Solution Approach 1:
The determination assist circuit implements feedback by continuously monitoring both the comparison determination signals from the dynamic comparator and the delayed clock signals. The OR circuits in the assist circuit receive these signals and generate determination assist signals that are fed back to the latch circuit. This feedback mechanism ensures that the AD conversion operation completes within the specified comparison period by forcing a determination result when the comparator output remains unchanged, thus maintaining high AD conversion completion rate while preserving independent operation capability.
Data Source
AI summary
In an AD converter circuit, a comparison circuit includes: a differential comparison circuit configured to perform comparison determination of differential input signals based on an internal clock signal and generate first differential output signals indicating a determination result; a determination assist circuit configured to receive the first differential output signals and generate second differential output signals; a latch circuit configured to hold the second differential output signals and generate third differential output signals; and a clock generation circuit configured to generate the internal clock signal based on the third differential output signals. The determination assist circuit varies a value of the first differential output signals and generate the second differential output signals when a designed time has elapsed with values of the first differential output signals being unvaried from a reset value since the start of an operation of the comparison determination in the differential comparison circuit.