SAR ADC Comparator Timing to Avoid Metastable Output States
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Solution Overview
Problem
Conventional successive approximation A/D converters can fall into metastable states when the voltage difference between the storage node and the reference voltage is within 1 LSB or less, leading to unstable output signals and failure in A/D conversion.
Innovation Solution
A successive approximation A/D converter design that includes a capacitor array, multiple switch groups, and a comparator, where the control signal is generated to control the switch groups based on the judging output signal from the comparator, and a predetermined time is allowed for obtaining the judging output signal when the comparator cannot determine it at comparison timing, thereby avoiding metastable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the comparator performs voltage comparison at exact comparison timing, then the A/D conversion speed is improved, but the system falls into metastable states when voltage difference is within 1 LSB or less
Solution Approach 1:
The patent applies preliminary action by performing voltage comparison slightly before the exact comparison timing. The comparator compares the voltage at a timing earlier than the ideal moment, and the result is held until the required output timing. This prevents the metastable state issue while maintaining conversion speed, as the comparison is done in advance when the voltage difference is more clearly distinguishable.
2Reliability
If a predetermined time delay is introduced for obtaining the judging output signal, then metastable states are avoided, but the A/D conversion time increases
Solution Approach 1:
The patent performs the voltage comparison in advance before the exact comparison timing, and holds the result until the required output timing. This preliminary action approach eliminates the need for a time delay after comparison, as the comparison is already completed early. The conversion time is thus minimized while still avoiding metastable states.
3Reliability
If the comparator waits for a predetermined time after comparison timing to output the signal, then the output stability is improved, but the productivity of the A/D converter decreases
Solution Approach 1:
The patent performs the comparison operation in advance before the required output timing, rather than waiting after comparison. The comparator compares voltages early, and the result is held in a storage element until the exact output timing is reached. This eliminates the productivity-reducing wait time while ensuring stable output, as the comparison is completed with sufficient margin before the deadline.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design ensures a robust successive approximation A/D converter that does not fall into metastable states, facilitating easy semiconductor integration and stable A/D conversion by allowing a controlled delay for voltage comparison.
Implementation Method 1
one capacitor 106_1 whose capacitance value is set to a predetermined reference capacitance C is provided in this successive approximation A/D converter. Further, (n−2) capacitors 106_2 to 106_(n−1), each of which is set to have each of capacitances C/2 to C/2 (n−2) obtained by weighting the above reference capacitance C with the reciprocals of powers of 2
Implementation Method 2
a comparator 104 connected to the capacitor array 106 to make a successive comparison in response to timing control signal CLK to obtain a judging output signal DO
Data Source
AI summary
The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.