SAR ADC Dynamic Element Matching for Capacitor Mismatch Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive approximation register analog to digital converters face errors due to capacitor mismatch caused by process and temperature variations, leading to non-linearity, which traditional designs attempt to address by using large capacitors or oversampling, resulting in increased circuit area or limited signal frequency.
Innovation Solution
The implementation of a successive approximation register analog to digital converter device that includes a first and second digital to analog converter circuit, a comparator circuit, and a dynamic element matching circuit, which samples an input signal, generates comparison results, encodes bits to refresh the converter circuit, and resets bits to improve linearity without increasing circuit area or limiting signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large capacitor is employed to reduce mismatches, then manufacturing precision is improved, but area of stationary object increases
Solution Approach 1:
The capacitor array is segmented into multiple sub-arrays, each with smaller capacitors. The dynamic element matching circuit selectively activates different sub-arrays to achieve the desired capacitance values, avoiding the need for a single large capacitor while maintaining precision.
Solution Approach 2:
The patent employs dynamic element matching where the capacitor array configuration is dynamically adjusted during operation. The controller circuit selectively connects different capacitor subsets based on calibration data, allowing the system to adapt to process variations without requiring oversized fixed capacitors.
2Manufacturing precision
If an over sampling technique is utilized to reduce the error, then manufacturing precision is improved, but frequency of moving object is limited
Solution Approach 1:
The patent performs preliminary calibration of the capacitor array before normal operation. During calibration, the system characterizes capacitor mismatches and stores correction data. This preliminary action eliminates the need for continuous oversampling during signal conversion, thereby maintaining high input frequency capability while achieving high precision.
Solution Approach 2:
The system implements a feedback mechanism where calibration results are used to adjust subsequent conversion operations. The controller circuit uses stored calibration data to compensate for capacitor mismatches in real-time, reducing conversion errors without requiring oversampling and thus preserving high-speed operation.
Data Source
AI summary
A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.