SAR ADC Capacitor Mismatch Measurement by Oscillation Counting
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Solution Overview
Problem
High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in accurately measuring capacitor mismatch, particularly for low-value capacitors in large arrays, due to limitations in test structures, simulation, noise, precision, and stability of test equipment.
Innovation Solution
The integration of capacitor mismatch measurement circuitry, including a first and second relaxation oscillator, counter circuitry, and switching mechanisms, allows for the determination of capacitance differences by counting cycles during a predetermined time interval, enabling effective compensation for capacitor mismatches and improving ADC accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution SAR ADC is implemented by increasing the number of bits, then the resolution is improved, but the size of the largest binary-valued capacitor significantly increases
Solution Approach 1:
The capacitor array is segmented into multiple groups, with each group containing capacitors of the same binary weight value. This segmentation allows for independent measurement and compensation of mismatch errors within each group, reducing the overall impact of capacitor size variations on ADC resolution.
Solution Approach 2:
The invention changes the measurement parameter from direct voltage comparison to frequency-based oscillation counting. By measuring the number of oscillation cycles of a test oscillator during a fixed time interval, the system can accurately determine capacitor mismatch ratios without being directly affected by the absolute capacitor sizes, thus resolving the contradiction between high resolution and large capacitor dimensions.
2Ease of operation
If traditional test structures and simulation methods are used to measure capacitor mismatch, then the measurement process is simple, but the measurement precision deteriorates due to noise and equipment limitations
Solution Approach 1:
The invention replaces traditional voltage-based measurement methods with a frequency-based oscillation counting method. The test oscillator converts capacitor mismatch into frequency differences, which are then measured by counting oscillation cycles during a predetermined time interval. This substitution eliminates the need for high-precision voltage measurement equipment and reduces susceptibility to noise, thereby improving measurement precision while maintaining operational simplicity.
3Adaptability or versatility
If external test equipment is used to measure capacitor mismatch, then the measurement setup is external, but the measurement stability deteriorates
Solution Approach 1:
The invention implements self-service measurement by integrating the test oscillator and measurement circuitry directly within the ADC device. The test oscillator uses the same capacitor array under test, allowing the system to measure its own capacitor mismatches without external equipment. This internalization improves measurement stability by eliminating external interference and ensuring consistent operating conditions, while still maintaining adaptability through programmable measurement control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise measurement and compensation of capacitor mismatches, enhancing the accuracy and reliability of high-resolution SAR ADCs by reducing inaccuracy caused by capacitance variations, thereby improving the overall performance of the ADCs.
Implementation Method 1
a first relaxation oscillator to switchably connect to the selected capacitor and output a clock signal at a frequency that is a function of the capacitance of the selected capacitor
Implementation Method 2
a counter circuitry to count a number of cycles output by the first relaxation oscillator during a predetermined time interval generated by a second relaxation oscillator
Data Source
AI summary
An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.