SAR ADC DAC Array Layout for Bottom-Plate Mismatch Shaping

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing SAR ADCs face challenges in achieving high linearity and accuracy due to manufacturing errors in capacitors, particularly when using bottom plate sampling and mismatch error shaping is incompatible with binary scaling.

Innovation Solution

An ADC design that incorporates multiple DAC arrays, including a first DAC array for MSBs and two LSB DAC arrays, which alternate configurations to enable bottom-plate sampling and mismatch error shaping, reducing errors through data weighted averaging and mismatch error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Data Weighted Averaging (DWA) is used for the MSB to increase linearity, then the linearity performance is improved, but the method is only useful for thermometric DACs and not compatible with binary scaling DACs

Engineering Contradiction:

ImprovelinearityVSAvoidcompatibility with binary scaling

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent divides the DAC into two separate arrays: a first DAC array for MSBs and a second DAC array for LSBs. This segmentation allows each array to be optimized for its specific function - the first array can use DWA for improved linearity while the second array handles binary scaling, thus resolving the compatibility issue.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If conventional Mismatch Error Shaping (MES) is used to increase linearity, then the linearity is improved, but the method is only compatible with top plate sampling and not bottom plate sampling

Engineering Contradiction:

ImprovelinearityVSAvoidcompatibility with bottom plate sampling

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent inverts the conventional MES approach by sampling the bottom plate of the capacitors rather than the top plate. This inversion allows MES to be compatible with bottom plate sampling architecture while maintaining its error-shaping functionality, thus resolving the compatibility contradiction.

Inventive Principle:

Principle #13The other way round (Inversion)

3Measurement precision

If multiple DAC arrays are used to enable bottom plate sampling and mismatch error shaping, then linearity and accuracy are significantly enhanced, but the device complexity increases

Engineering Contradiction:

ImprovelinearityVSAvoidnumber of DAC arrays

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent designs the second DAC array to serve multiple functions: it provides LSB conversion and simultaneously enables mismatch error shaping when combined with bottom plate sampling. This multi-functionality reduces the need for additional dedicated circuits, thereby mitigating the complexity increase despite using multiple DAC arrays.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260113052A1Analog-to-digital conversion

Publication Date: 2026.04.23 GOOGLE LLC

AI summary

Methods, systems, and apparatus, for an analog-to-digital converter. One system includes an MSB DAC array configured to generate respective sample values for one or more most-significant bits of an output ADC value, a first LSB DAC array configured to generate respective sample values for one or more least-significant bits of the output ADC value, a second LSB DAC array configured to generate respective sample values for the one or more least-significant bits of the output ADC value, wherein each DAC array in the first LSB DAC array and the second LSB DAC array is configured to alternate between generating an output ADC bit value and a mismatch error value for the output ADC bit value.