SAR ADC Digital Calibration for Missing Code Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SAR ADCs suffer from systematic and random capacitor mismatch leading to integral and differential non-linearity, resulting in missing codes that negatively impact the signal-to-noise ratio and cause image artifacts in imaging systems.
Innovation Solution
A digital calibration circuit system comprising a first calibration circuit to correct systemic mismatch and a second calibration circuit to correct random mismatch, which identifies and compensates for missing codes by generating weights to correct the ADC output, and further utilizes a dither algorithm to randomize codes and reduce non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitor mismatch correction is implemented, then non-linearity is reduced, but device complexity increases
Solution Approach 1:
The calibration circuit is divided into two independent modules: a first calibration circuit for systematic mismatch correction and a second calibration circuit for random mismatch correction. Each module handles a specific type of error independently, allowing the complex calibration task to be segmented into manageable parts that can be implemented and tested separately while collectively achieving comprehensive linearity improvement.
Solution Approach 2:
The calibration circuits perform preliminary correction of capacitor mismatch errors before the main ADC conversion process. By pre-characterizing and storing correction weights in lookup tables during manufacturing or initialization, the actual conversion process can directly apply these pre-computed corrections without real-time complex calculations, reducing operational complexity while maintaining high precision.
2Reliability
If digital calibration circuits are added, then missing codes are resolved, but manufacturing complexity increases
Solution Approach 1:
Instead of implementing complex real-time correction logic, the patent uses lookup tables that store pre-computed correction weights. These tables are generated once during manufacturing or calibration and then copied/reused across multiple conversion operations. This approach trades one-time manufacturing complexity for simplified operational simplicity, making the system easier to manufacture while ensuring complete code coverage.
3Ease of manufacture
If capacitor tolerance is relaxed, then manufacturing cost decreases, but integral non-linearity increases
Solution Approach 1:
The patent implements a feedback mechanism where the actual capacitor values are measured during calibration, and correction weights are computed based on the measured deviations. These weights are stored and applied during normal operation to compensate for the relaxed tolerance capacitors. This feedback loop allows the use of lower-cost, higher-tolerance capacitors while maintaining high measurement precision through digital correction.
Data Source
AI summary
Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.