SAR ADC Capacitor DAC Layout for Lower MSB Switching Energy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analogue-to-digital converters, particularly those using successive approximation register (SAR) architecture with binary weighted capacitive DACs, consume high energy due to the charging and discharging of large capacitors, especially for determining the most significant bit, which results in significant power dissipation.
Innovation Solution
The proposed solution involves using a digital-to-analogue converter with a combination of equal capacitors for determining the most significant bits via a thermometer coded signal and binary weighted capacitors for the remaining bits, employing a hybrid search algorithm that minimizes the discharge of large capacitors, thereby reducing energy consumption. This approach includes splitting binary DACs into sub-DACs coupled by an addition circuit to manage capacitor mismatch and using a slope search for the most significant bits and a binary search for the lower bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a binary weighted capacitive DAC is used for determining the most significant bit, then the conversion speed is improved, but the power consumption increases significantly due to charging and discharging large capacitors
Solution Approach 1:
The patent divides the DAC capacitor array into two distinct portions: a first portion with equal capacitors for determining the most significant bit, and a second portion with binary weighted capacitors for determining the remaining bits. This segmentation allows the equal capacitor portion to use a thermometer coded signal that avoids discharging large capacitors, thereby reducing power consumption while maintaining conversion speed through the binary weighted portion.
2Use of energy by moving object
If a thermometer coded signal is used for the first portion of the DAC, then the energy consumption is reduced by avoiding capacitor discharge, but the device complexity increases
Solution Approach 1:
The patent segments the DAC into two portions with different coding schemes. The first portion uses thermometer coding with equal capacitors to minimize energy consumption for MSB determination, while the second portion uses binary weighting for the remaining bits. This segmentation balances energy efficiency with acceptable device complexity by applying different optimization strategies to different parts of the system.
Solution Approach 2:
The patent applies different local qualities to different portions of the DAC: the first portion is optimized for energy efficiency using equal capacitors and thermometer coding, while the second portion is optimized for compactness and speed using binary weighted capacitors. This local differentiation allows each portion to excel at its specific function without compromising the overall system performance.
3Device complexity
If binary weighted capacitors are used, then the number of capacitors is reduced, but the manufacturing precision requirements increase due to capacitor mismatch
Solution Approach 1:
The patent segments the capacitor array so that the first portion uses equal capacitors (which are less sensitive to mismatch for thermometer coding) while the second portion uses binary weighted capacitors. This segmentation allows the system to benefit from the reduced capacitor count of binary weighting while mitigating the mismatch issue by using equal capacitors for the critical MSB determination where precision is most important.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces power consumption by minimizing the energy wasted in charging and discharging capacitors, achieving lower overall energy dissipation during the analogue-to-digital conversion process while maintaining efficient conversion speed.
Implementation Method 1
a comparator for comparing the input signal with a reference signal and producing a comparator output signal
Implementation Method 2
the digital-to-analogue converter at least comprises a first portion implemented with equal capacitors
Data Source
Figure 1~3
Figure 4~5
AI summary
The present invention is related to an analogue-to-digital (A/D) converter (1) for converting an input signal (Vin) to a digital code representing said input signal. The A/D converter comprises a comparator (3) for comparing the input signal with a reference signal (VA), a search logic block (4) for determining the digital code and a digital-to-analogue converter (5) arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. The digital-to-analogue converter comprises at least a first portion implemented with equal capacitors (20). The ADC optionally further comprises a second portion implemented with binary weighted capacitors. The first portion is arranged for being controlled by a thermometer coded signal. The converter avoids charging-discharging of large capacitors during the search and therefore reduces the lost energy.