SAR ADC MSB/LSB Conversion Split for Fast Reference Settling
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Solution Overview
Problem
Conventional SAR ADCs face limitations in high-resolution applications due to large input loading from multiple capacitive DACs and slow conversion rates, which restrict their use to low-bandwidth applications and are further hindered by complex routing and settling time issues in resistive DAC-based designs.
Innovation Solution
An analog-to-digital conversion apparatus using a comparator circuit to compare an analog input signal with reference levels, where the most significant bit is determined without successive approximation and the least significant bit is estimated through a successive approximation procedure using multiple reference levels, reducing the need for multiple capacitive DACs and minimizing switching requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple capacitive DACs are used for 2-bit SAR ADC, then conversion rate can be extended to hundreds of MHz, but large input loading is generated which constrains higher resolution applications
Solution Approach 1:
The patent segments the ADC conversion process into two distinct phases: a preliminary comparison phase for MSB determination that operates without successive approximation, and a subsequent SAR phase for LSB determination. This segmentation allows the MSB conversion to complete rapidly without the iterative overhead of traditional SAR, thereby increasing overall conversion rate while reducing the resolution-dependent loading complexity
Solution Approach 2:
The patent performs preliminary comparison of the analog input signal against reference levels to determine the MSB portion before initiating the successive approximation procedure. This preliminary action establishes the coarse conversion result early, allowing the subsequent SAR process to focus only on the remaining LSB precision requirements, thus reducing both conversion time and the complexity of DAC routing for high-resolution applications
2Use of energy by moving object
If conventional SAR ADC operation is used, then power efficiency is excellent, but several clock cycles are required to complete one bit conversion limiting it to low-bandwidth applications
Solution Approach 1:
The patent dynamically adapts the conversion process by applying successive approximation only to the LSB portion after MSB has been determined through preliminary comparison. This dynamic approach maintains the power efficiency of SAR operation for the precision-critical LSB conversion while significantly reducing the total conversion time by excluding MSB from the iterative process, thereby enabling high-bandwidth applications
3Device complexity
If resistive DAC-based design is employed to alleviate capacitive loading, then input loading problem may be reduced, but large number of switches and complex routing limits references settling time and conversion rate
Solution Approach 1:
The patent segments the reference voltage requirements into two groups: reference levels for preliminary MSB comparison that require fast settling, and reference levels for subsequent SAR LSB conversion. By separating these reference requirements temporally and functionally, the system can use simpler resistive DAC structures without suffering from prolonged settling time penalties, as the critical MSB comparison completes before full settling is required
Data Source
AI summary
A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.