SAR ADC MSB Capacitor Switching for Fast Low-Distortion Conversion
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face performance degradation when dealing with analog input signals that have a smaller voltage range than the supply voltage, leading to increased rise times and reduced speed due to the need for external reference voltages and power consumption, and existing solutions either impact area and power considerations or introduce linearity errors.
Innovation Solution
Configuring the most-significant bit capacitor of the internal DAC to take input from the supply voltage VDD instead of the reference voltage VREF, allowing for faster voltage development and simplifying the VREF design, while also driving more significant bits with VDD to increase speed and reduce capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external reference voltage VREF is used for ADC conversion, then conversion accuracy is maintained, but rise time increases and speed decreases
Solution Approach 1:
The capacitor bank is segmented into two groups: capacitors associated with more significant bits (MSBs) that are driven by supply voltage VDD, and capacitors associated with less significant bits (LSBs) that are driven by reference voltage VREF. This segmentation allows the MSBs to charge faster (improving speed) while the LSBs maintain precision (preserving accuracy).
Solution Approach 2:
Different voltage sources are applied to different parts of the capacitor bank based on their significance. The MSB capacitors use VDD for faster charging, while the LSB capacitors use VREF for higher precision. This local differentiation optimizes both speed and accuracy in their respective domains.
2Stability of the object's composition
If all capacitors are driven by reference voltage VREF, then linearity is maintained, but area and power consumption increase
Solution Approach 1:
The capacitor bank is divided into two segments driven by different voltage sources. By segmenting the capacitor bank and applying VDD to MSBs, the total capacitance required can be reduced while maintaining the necessary resolution and linearity through the weighted sum of the segmented parts.
Solution Approach 2:
The voltage parameter is changed from VREF to VDD for the MSB capacitors. This parameter change allows for smaller capacitor sizes in the MSB section while maintaining overall conversion accuracy, thereby reducing total area and power consumption.
3Speed
If supply voltage VDD is used for all capacitors, then speed increases, but linearity errors are introduced
Solution Approach 1:
The capacitor bank is segmented by bit significance, with MSBs driven by VDD for speed and LSBs driven by VREF for linearity. This segmentation allows the system to exploit the speed advantage of VDD where it matters most (MSBs) while preserving linearity in the LSBs.
Solution Approach 2:
Different voltage sources are applied locally to different capacitor groups based on their position in the binary weight hierarchy. The local quality of each capacitor group is optimized: MSBs prioritize speed with VDD, while LSBs prioritize linearity with VREF.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 500% increase in speed with 25% of the area and significantly smaller decoupling capacitors, maintaining consistent performance and simplifying the design while reducing power consumption.
Implementation Method 1
a capacitor network having a first capacitor and a plurality of second capacitors, the first capacitor being coupled to a first line carrying a first voltage and a second line carrying a second voltage, and the plurality of second capacitors being coupled to the second line and to a third line carrying a third voltage
Data Source
AI summary
An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB. The DAC further including and a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors. And the second capacitors are associated with less significant bits, and an input voltage line carrying an input voltage (VIN) switchably coupled to the first input or switchably coupled to the second input.