SAR ADC Capacitive Sampling Architecture for Multi-Input Throughput

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

High-speed SAR ADCs face challenges in processing multiple inputs efficiently due to speed limitations and potential mismatch errors when using multiplexers, which can compromise conversion speed and introduce measurement errors.

Innovation Solution

The implementation of multiple parallel capacitive sampling circuits that can independently track each input, allowing for high ADC throughput rates and improved common-mode rejection, while separating sampling and feedback capacitors to operate in different voltage domains, enabling rail-to-rail input range and simultaneous sampling without speed or mismatch issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a multiplexer is used to process multiple inputs in a high-speed SAR ADC, then the ADC can handle multiple input signals, but speed limitations and mismatch errors occur that compromise conversion speed and introduce measurement errors

Engineering Contradiction:

Improvemultiple input processing capabilityVSAvoidconversion accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent divides the single ADC processing path into multiple parallel capacitive sampling circuits, each dedicated to one input signal. This segmentation eliminates the need for a multiplexer by providing dedicated sampling paths, thereby maintaining high conversion speed and accuracy for multiple inputs simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal feedback path that serves all multiple input signals. The feedback capacitor and DAC share a common feedback path that can process feedback signals for any of the multiple inputs, enabling the system to handle multiple inputs with a single feedback mechanism, thus improving efficiency without sacrificing precision.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If multiple parallel capacitive sampling circuits are implemented, then high ADC throughput and improved common-mode rejection are achieved, but circuit complexity increases

Engineering Contradiction:

ImproveADC throughput rateVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple sampling circuits into a unified architecture where all capacitive sampling circuits share a common feedback path, including a shared feedback capacitor and DAC. This merging approach allows multiple inputs to be processed in parallel while reducing overall circuit complexity compared to having completely separate processing paths for each input.

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If sampling and feedback capacitors are separated to operate in different voltage domains, then rail-to-rail input range is enabled and measurement accuracy improves, but device complexity increases

Engineering Contradiction:

Improveinput range accuracyVSAvoidvoltage domain management

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies different voltage domain characteristics to different parts of the circuit: the capacitive sampling circuits operate in one voltage domain optimized for sampling, while the feedback path operates in another voltage domain optimized for feedback control. This local differentiation of voltage domains allows each part to be optimized for its specific function, improving overall measurement precision.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high-speed, high-accuracy analog-to-digital conversion for multiple inputs with improved common-mode rejection and expanded single-ended dynamic range, maintaining high ADC throughput even with relatively slow inputs, and reducing power consumption and circuit costs.

Implementation Method 1

Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

The comparator is configured to produce a digital value corresponding to the at least one input signal

Methodology Applied

Scientific EffectVoltage comparison:

Implementation Method 3

The method further includes producing a digital code related to the digital value using a successive approximation register

Methodology Applied

Scientific EffectDigital approximation:

Data Source

PatentUS8952839B2Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method

Publication Date: 2015.02.10 SILICON LABORATORIES INC

AI summary

A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.