SAR ADC Multi-Sampling for Higher Resolution Bit Modes
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Solution Overview
Problem
SAR analog-to-digital converters are typically limited to operating in a fixed N-bit mode, and there is a need for them to operate in varying bit modes to achieve higher resolution without requiring increased hardware complexity.
Innovation Solution
The method involves taking multiple samples for each analog value and adding a portion of the least significant bit (LSB) to all but one of the samples, accumulating and outputting these samples as a digital value with resolution greater than the N-bit capability of the SAR ADC, using dynamic threshold adjustments and element matching to enhance linearity and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple samples are taken and accumulated to achieve higher resolution, then measurement precision is improved, but loss of time increases due to multiple sampling cycles
Solution Approach 1:
The patent performs preliminary actions by taking multiple samples and accumulating them in advance through the accumulator circuit. The multiple samples are captured and stored during different time periods, then combined through accumulation to achieve higher effective resolution. This preliminary accumulation of data allows the system to achieve 12-bit resolution from an 11-bit ADC without requiring real-time complex processing, thus managing the time trade-off.
2Adaptability or versatility
If capacitor array is reconfigured to achieve higher bit modes, then adaptability is improved, but device complexity increases due to additional switching control
Solution Approach 1:
The patent implements dynamic reconfiguration of the capacitor array by controlling the switching network to connect capacitors in different configurations based on the desired bit mode. The switching network dynamically adjusts the capacitor connections during operation, allowing the ADC to switch between 10-bit, 11-bit, and 12-bit modes. This dynamic approach enables adaptability without requiring completely separate hardware for each mode, as the same physical capacitors are reconfigured through controlled switching.
Solution Approach 2:
The capacitor array serves multiple functions by operating in different bit modes (10-bit, 11-bit, 12-bit) using the same physical hardware. The switching network enables the capacitor array to be universally applicable across different resolution requirements, eliminating the need for separate capacitor arrays for each bit mode. This multi-functionality reduces overall device complexity compared to having dedicated hardware for each operating mode.
3Device complexity
If N-bit SAR ADC is used to achieve greater than N-bit resolution, then device complexity is reduced, but manufacturing precision requirements increase to maintain linearity
Solution Approach 1:
The patent employs feedback mechanisms through the successive approximation register (SAR) and comparator to achieve high effective resolution. The SAR circuit performs iterative comparisons and adjusts the digital output based on feedback from the comparator, which compares the input voltage with the DAC output. This feedback-based successive approximation process allows the system to achieve 12-bit effective resolution from an 11-bit ADC by using software-controlled accumulation and averaging, reducing the need for extremely precise capacitor matching that would be required in a native 12-bit hardware implementation.
Solution Approach 2:
The patent uses multiple copies of the same ADC hardware (taking multiple samples) to achieve higher effective resolution. By accumulating multiple 11-bit samples through the accumulator circuit and applying dithering techniques, the system effectively creates virtual additional bits. This copying approach of taking multiple measurements and combining them mathematically achieves the goal of higher resolution without requiring proportionally more precise physical capacitor manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows SAR ADCs to operate in higher bit modes without the need for additional hardware, effectively increasing the resolution by averaging and matching capacitor configurations, thus achieving higher bit accuracy without the size and power consumption of a dedicated higher-bit converter.
Implementation Method 1
The DAC portion of the SAR ADC can utilize a capacitor network. Each of the capacitors in the switched capacitor DAC has one plate thereof connected to a common node
Implementation Method 2
A comparator determines whether the sampled analog value is above or below the DAC output, and the result (bit 1, the most significant bit of the conversion) is stored in the successive approximation register (SAR)
Data Source
AI summary
A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.