SAR ADC Reference Switching for Time-Varying Noise Rejection
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Solution Overview
Problem
SAR ADCs are susceptible to noise errors due to time-varying noise components in reference voltage sources, which affect the accuracy of the conversion process.
Innovation Solution
Introducing a VREF component to the NDAC during bit trials, allowing the differential comparator to reject noise as a common mode signal, thereby reducing noise errors by up to 50% and further embodiments achieving 25% or 12.5% reduction in noise errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the SAR ADC uses reference voltage sources VREF and VREF for the DAC arrays, then the conversion process can be performed, but time-varying noise components in these voltage sources introduce error to the conversion process
Solution Approach 1:
The patent connects the bottom plates of capacitors in the second DAC array to the VREF voltage source, creating equipotential regions that reject common-mode noise. By maintaining the same voltage potential across affected nodes, the circuit becomes immune to time-varying noise components on the reference voltage sources, thereby improving conversion accuracy without sacrificing functionality.
Solution Approach 2:
The patent converts the harmful noise effect into a beneficial common-mode signal. By intentionally introducing VREF connections to create common-mode voltage components, the noise appears equally on both differential inputs of the comparator, allowing the differential comparator to reject it as common-mode noise, thus transforming the harmful noise into a benefit for noise rejection.
2Object-affected harmful factors
If the bottom plates of capacitors in the second DAC array are connected to ground, then the circuit structure is simple, but noise rejection capability is reduced
Solution Approach 1:
Instead of connecting to ground, the bottom plates of capacitors in the second DAC array are connected to VREF, creating an equipotential reference that provides noise rejection. This maintains structural simplicity while enhancing noise rejection capability by utilizing the existing VREF voltage source already present in the circuit.
Solution Approach 2:
The VREF voltage source serves dual functions: it provides the reference voltage for the DAC operation and simultaneously acts as a noise rejection mechanism for the second DAC array. By making the bottom plates connect to VREF, the same voltage source performs multiple functions, avoiding additional circuit complexity while improving noise rejection.
Data Source
AI summary
An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREF signal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREF noise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.