Recycling Integrator SAR ADC for High-Order Noise Shaping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SAR analog-to-digital converters face limitations in high-order loop filter complexity, input impedance degradation, and non-linear characteristics, leading to increased power consumption and circuit noise, especially when dealing with biopotential signals in wearable healthcare devices.
Innovation Solution
A SAR analog-to-digital converter design that recycles a single amplifier for high-order integration, amplifies input impedance by reusing sampled information, and employs a clock-averaged element matching process to improve linearity, using a recycling integrator and digital-to-analog conversion controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of integrators is increased to design a high-order loop filter, then the system order and energy efficiency are improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent merges multiple integrator functions into a single integrator by time-multiplexing its operation. The single integrator performs integration for different bits at different time periods, effectively replacing what would traditionally require multiple parallel integrators. This merging approach achieves high-order noise shaping (improving energy efficiency) while maintaining low device complexity.
Solution Approach 2:
The integrator is designed to dynamically reconfigure its operation across different time periods. During first time period, it integrates for MSB; during second time period, it integrates for LSB. This dynamic time-multiplexed operation allows one integrator to perform the work of multiple integrators, resolving the contradiction between energy efficiency and complexity.
2Use of energy by moving object
If the number of comparator input terminals is increased to accommodate high-order loop filter, then the system order is improved, but the circuit noise increases
Solution Approach 1:
The patent combines multiple comparison operations into a single comparator by sequential time-multiplexed operation. The comparator first compares for MSB during the first time period, then compares for LSB during the second time period. This merging of comparison functions into one comparator maintains high system order while avoiding the noise increase that would result from having multiple parallel comparators with many input terminals.
Solution Approach 2:
The comparator dynamically switches between different comparison tasks at different time periods. It is configured to perform MSB comparison during the first time period and LSB comparison during the second time period. This dynamic operation allows the system to achieve high-order functionality with a single comparator, thereby minimizing circuit noise.
3Manufacturing precision
If a calibration process is applied to resolve DAC element mismatch, then the linearity is improved, but the power consumption and time increase
Solution Approach 1:
The patent incorporates calibration actions directly into the normal conversion operation flow. During the conversion process itself, the system performs calibration by switching capacitor connections and comparing voltages at different time periods. This preliminary integration of calibration into the conversion routine eliminates the need for separate calibration cycles, thereby improving linearity without significant time or power penalty.
Solution Approach 2:
The calibration process is made continuous with the conversion operation. Rather than performing calibration as a separate discrete step that stops normal operation, the system continuously performs both conversion and calibration functions by time-multiplexing them within the same operational framework. This continuity ensures linearity improvement while minimizing loss of conversion time.
Data Source
AI summary
The present invention relates to a successive approximation register (SAR) analog-to-digital converter and the SAR analog-to-digital converter according to an example embodiment includes an input unit including at least one SAR capacitor; a recycling integrator connected to the input unit and including k integration capacitors configured to store the respective residue information generated in an integration process performed k times, respectively, (where k denotes a positive integer of 2 or more) using a single amplifier; a comparator connected to an output terminal of the recycling integrator; and a SAR controller connected to an output terminal of the comparator and configured to generate a digital signal corresponding to output of the comparator.